搜索资源列表
BCD-youxianbianma
- 优先编码器，通过VHDL语言实现BCD优先编码的功能-Priority encoder BCD priority encoder function through VHDL language
HD6409_encode
- 基于VHDL语言的HD4069曼彻斯特编码器实现-Based on VHDL HD4069 Manchester encoder implementation
QDEC
- 旋转编码器的正交解码程序，使用VHDL语言--- This decoder in VHDL samples the signals using all four available edges of -- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on -- falling(A), and sample(A) on rising(B).
encoder
- 使用VHDL编写的光电编码器。并且在quartus软件进行仿真。最终下载在FPGA板上实现光电编码器的使用。-Optical encoder using VHDL written. And quartus software simulation. The final use of photoelectric encoder download FPGA board.
BCH
- 此代码用VHDL实现BCH(57,44,6)编码器，属于信道编码的内容，此外采用Miggitt译码器实现译码功能。-This code BCH (57,44,6) encoder using VHDL, is a channel coding content, the addition Miggitt decoder decoding function.
FSK
- vhdl编写的FSK编码器与解码器，绝对可用，拿去用吧。 -the FSK encoder and decoder VHDL written, absolutely free, and take with you.
VHDL
- HDB3码的编码解码器，根据HDB3码的编解码规则编的vhdl程序-failed to translate
82be270ea751
- RS（255，239）编码器的VHDL语言源代码，希望能对大家有一定帮助-the code of the encoder of rs（255,239），hope can help you
EDA
- VHDL 交通灯 奇偶校验器 编码器，教学所用-VHDL traffic lights parity encoder, teaching
bcd_adder
- 用vhdl实现的bcd编码器，实现bcd编码，实验程序，已经调试成功-To bcd encoder vhdl to achieve the bcd coding, experimental procedures, debugging has been successful
Verilog
- VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等-VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等
coder83
- 基于VHDL的8-3优先编码器模块，din0-din7八位二进制输入编码后输出三位编码结果。采用正逻辑设计，高电平有效。-8-3 priority encoder module, based on VHDL din0- din7 eight binary input encoded output three coding results. Adopt positive logic design, high level effectively.
t2_manchester_coder
- Manchester 编码器的Verilog与VHDL实现，并分别采用moore和mealy机对其进行描述，比较了两种实现方法的不同。并且每种情况都给出了测试脚本，希望对您有用。-Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And
卷积码、CRC
- 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
rs(63-45)
- 用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。-VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.
biss_master_ad36_1217
- biss-c编码器读代码，测试好用，时钟要求40m -VHDL code about biss-c slave part.
arm_FPGA
- 步进电机、直流电机PWM控制、伺服电机编码器解码vhdl程序-Stepper motor, PWM DC motor control, servo motor encoder decoder VHDL program
shifter
- 用vhdl语言采用时序电路(移位寄存器)的方式实现（7，4）循环码编码器-Vhdl language used by the timing circuit (shift register) way to achieve (7,4) cyclic code encoder
Priority-encoder
- 用VHDL语言编程来实现优先编码器的功能。-VHDL language programming to achieve priority encoder function.
HDB3
- 大三学生完成 基于VHDL的HDB3编码器设计-HDB3 encoder juniors complete VHDL-based design