搜索资源列表
123654vhaing
- 八音自动播放电子琴设计 vhdl源码，文件内有具体注释 [VHDL-XILINX-EXAMPLE26.rar] - [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9- -Octave electronic keyboard play aut
EDA
- EDA实验序列信号检测器和模可变计数器，工程文件和VHDL文件-EDA test sequence signal detector and variable-counter model, project files and VHDL files
shipintuxiang
- 基于VHDL，实现视频图像的行列计数器，已经调试仿真通过可用.-Based on VHDL, the ranks of video image counter, has been simulated through the available debugging.
pinglvji
- 做的等精度频率计，采用等精度测量原理，即利用双计数器“相关计数”和“硬件同步分频”实现高低频率的等精度的测量。用FPGA实现频率测量、周期测量、时间间隔测量、相位测量及脉冲宽度的测量。所有的测量功能都由VHDL语言编程实现。-I do other precision frequency meter, use and other precision measuring principle, namely the use of dual-counter " related counts&qu
cnt10
- 一个用VHDL语言编写的十进制计数器，后续还有分频器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -VHDL language us
cnt
- 俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials
Timer
- 基于ｖｈｄｌ的电子时钟，其中包括六进制计数器和十进制计数器。-VHDL-based electronic clock, including six hexadecimal decimal counters and counters.
SCHK
- 实验图1是一含计数使能、异步复位和计数值并行预置功能4位加法计数器，例1是其VHDL描述。由实验图1所示，图中间是4位锁存器；rst是异步清信号，高电平有效；clk是锁存信号；-Figure 1 is a test with count enable, asynchronous reset and preset features include numerical parallel adder four counters, Example 1 is described in VHDL. By e
cnt10
- vhdl 十进制加法计数器设计 已经调试成功-decimal adder vhdl counter the success of design debugging
jishuqi
- 电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed
count999
- vhdl实现的计数器,可以从0记到999,该代码使用模块化设计思想,开发工具muxplus2-achieved vhdl counter, can be recorded from 0 to 999, the code uses the modular design concept, development tools muxplus2
m8
- 这是一个8分频的VHDL语言设计程序，也可以看成是8进制计数器-This is an 8-frequency design process of the VHDL language can also be seen as a hexadecimal counter 8
MY
- 计数器和译码器的程序，基于EDA的VHDL语言-Counter and decoder procedures, based on the VHDL language EDA
counter
- 运用VHDL语言实现的，功能是实现可控计数器。-The use of VHDL language, the function is to achieve controllable counter.
count10
- 基于Quartus II的十进制加法计数器的项目设计，包含了项目文件和VHDL源代码-Quartus II based on the decimal adder counter the project design, including project documents and VHDL source code
bcd
- EDA 十进制计数器、BCD VHDL源代码-EDA decimal counter VHDL source code
singt
- 用VHDL语言描述的用锁存器，加法计数器，ROM存储器构成的RTL图-VHDL language used to describe the use of latches, adding counters, ROM memory map consisting of RTL
22
- 使用VHDL实现16进制的计数器的算法程序-Use VHDL to achieve 16 of the counter-band algorithm procedure
counter
- 这是用VHDL设计的十进制计数器，两个VHDL程序分别说明了out和buffer的区别-It is designed with VHDL decimal counter, the two VHDL procedures were illustrated the difference between out and buffer
100VHDLexample
- VHDL编程中常用到的100个例子的源程序包括四输入多路器，信号驱动源，寄存／计数器等，使用非常方便。-VHDL programming of commonly used example of the source 100 includes a four-input multiplexer, the signal driver source, storage/counter, etc., very convenient to use.