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ENT6
- 加法计数器的VHDL工程,程序,仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU
count
- VHDL语言编写的计数器程序,实现1到9999计数,并动态扫描显示,带清零和暂停功能,课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs
paomadenghe60jinzhi
- 一个用VHDL编写的跑马灯程序和60进制计数器的程序,一个是自己设计的一个是老师要求,都在实验箱上验证成功,希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.
count
- 用VHDL编写的4、7、40、64、84计数器,可将程序中的具体数字设成任意值。-Using VHDL written 4,7,40,64,84 counter, you can program specific figures set to any value.
shizhong4
- 用VHDL语言设计的24小时计数器,并在数码管上显示-VHDL language design with 24-hour counters, and digital tube display
jishuqivhdl
- 使用 VHDL 描述计数器的设计、综合、仿真的全过程,能够实现多重功能-Counter design using the VHDL descr iption, synthesis, simulation of the whole process to achieve multi-functionality
updown_6
- 这是一个使用VHDL语言编写的六进制计数器,具有自动控制加计数或减计数的功能。-This is a VHDL language using the six binary counter, with automatic control plus or minus count count function.
counter_12
- 使用VHDL语言编写的十二进制计数器,有异步清零、同步置数的功能、-Using the VHDL language of the 10 binary counter, there are asynchronous clears, synchronous set the number of functions,
taxi-VHD
- 出租车计数器的VHDL编程源码,包含整个工程文件-出租车计数器的VHDL编程源码
xyz123
- 用VHDL写的60进制计数器 用VHDL写的60进制计数器-Written in VHDL, using 60 binary counter binary counter 60 written in VHDL using VHDL written in 60 binary counter
bianbuchangjiajiancount
- 源码,VHDL语言编写的可变步长加减计数器-VHDL language variable-step addition and subtraction counter
count10
- 基于vhdl语言的10进制的计数器程序,应该有用-Vhdl-based language program for 10 binary counter
VHDLscounter
- 通过VHDL自行设计的一个秒表共有4个输出显示,分别为、十分之一秒、秒、十秒、分,所以共有4个计数器与之相对应(3个十进制计数器,一个6进制计数器用来对十秒进行计数),整个秒表还需有一个复位信号和一个精确的10HZ时钟信号。-Of a self-designed by VHDL stopwatch showed a total of four outputs, namely, one-tenth of seconds, seconds, ten seconds, minutes, so a to
speed_test
- QuartusII运行环境下的计数器的VHDL源代码,其中有部分文档说明。-QuartusII operating environment under the counter VHDL source code, some of them documented.
example3
- 加减法计数器: 本例程为加减法计数器,主要实现的加减法计数的功能。 有3个控制端口: 1、rst复位控制低电平有效; 2、en使能控制高电平有效 3、up加/减控制,高电平加法,低电平减法。-vhdl
cnt4_10
- 用VHDL在FPGA开发板上实现4位十进制计数器 -Use VHDL to achieve 4-bit decimal counter
counter
- vhdl编写计数器,打开可用,有进位 vhdl编写计数器,打开可用,有进位-vhdl preparation counter, open the can, there are binary vhdl preparation counter, open the can, there are binary
jtd2
- 基于VHDL状态机设计的智能交通控制灯 总体设计结构框图如图2所示,共有11个功能模块,包括控制东西方向交通灯的状态机和控制南北方向交通灯的状态机、计数器模块、键盘扫描模块、数字合成模块、三个分位模块、数码管显示模块、动态显示扫描模块。-VHDL-based state machine design of intelligent traffic control lights
experiment6
- VHDL课程实验6,数控分频器的设计。对应不同的输入信号,预置数(初始计数值)设定不同的值,计数器以此预置数为初始状态进行不同模值的计数,当计数器的状态全为1时,计数器输出溢出信号。用计数器的溢出信号作为输出信号或输出信号的控制值,使输出信号的频率受控于输入的预置数-VHDL course experiment 6, NC Divider. Corresponding to different input signals, the set value (initial count) to set
CNT4
- 4位二进制加法计数器的两种不同VHDL的描述,与比较。-4-bit binary addition of two different counter VHDL descr iption, and more.