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generate-coordinates
- 使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。-Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive numb
VHDL_design
- 本综合实验包括节拍脉冲发生器、键盘扫描显示和八位二进制计数器三个模块。采用VHDL语言为硬件描述语言，Xilinx ISE 10.1作为开发平台，所开发的程序通过调试运行验证，初步实现了设计目标。-This includes comprehensive experimental beats pulse generator, display and keyboard scan eight binary counter three modules. Using VHDL as the hardwar
danweitaichufaqi
- 用VHDL实现了单稳态触发器的计数器功能，配合单稳态触发器中的D触发器可以实现单稳态触发器功能。-Using VHDL realize counter function of monostable trigger, D trigger monostable trigger monostable trigger function can be achieved.
the-realization-of-sin
- 利用VHDL语言，实现正弦波的产生，在此程序中，利用计数器原理实现-Using VHDL language, sine wave generation, in this procedure, the use of counter principle to achieve
Verilog
- VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等-VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等
sy
- 利用VHDL语言设计的电子数字钟，有时、分钟、秒钟计数器、还有整点报时报警。-Design using VHDL language electronic digital clock, sometimes, minutes, seconds counter, as well as the whole point timekeeping alarm.
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
CNT10
- 通过Quartus II 软件，VHDL语言实现10进制计数器-Achieve 10 binary counter
Counter
- 用VHDL设计具有清除端、使能端，计数范围为0-999的计数器设计。输出为8421BCD码-VHDL design with a clear end to enable the end, the design for the counter counting range 0-999. 8421BCD code output
74LS160jishuqi
- 74ls160十进制可预置计数器VHDL语言代码-74ls160 decimal VHDL language code can be preset counter
counter4
- 计数器 基于xilinx ise硬件描述语言-counter VHDL
cny24
- 24进制加法计数器适用于vhdl和quartus-24 binary adder vhdl counter applied and quartus
100hexadecimalcounter
- 用vhdl对GAL22V10进行编程，实现100进制计数器-Using VHDL programming on GAL22V10, 100 hexadecimal counter
scan_led3
- 用VHDL语言写的数码管扫描电路。压缩包中还包括多路复用器、译码器和计数器。-VHDL language used to write the digital scanning circuit. Compressed package also includes multiplexers, decoders and counters.
Example23
- 设计一款多功能数字秒表的VHDL小程序，产生100Hz时钟的分频计数器-Design a multi-function digital stopwatch VHDL applet, generate 100Hz clock divider counter
EDA_frequency
- 非常好的程序，VHDL写的测频程序。适合做测频测相，多功能计数器。适合电赛的学生下载-Very good program
Counter
- 通过VHDL编程，在FPGA上实现计数器1至16的计数功能-Count from 1 to 16 by VHDL on FPGA
shuzizhong
- 数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
ones_counter
- 8bit 的计数器，如文件名所示microprogram_controlled_ones_counter_constraints_ise6_bak。VHDL-8bit counter, as shown in the file name. VHDL
counter_
- VHDL源代码+工程，可改变时钟的计数器-VHDL source code+ project, can change the clock counter