搜索资源列表
JiShuQi
- 实现了一个秒表计数器，输入为2MHZ时钟，使用VHDL语言实现-It implements a stopwatch counter input 2MHZ clock, using VHDL language
cpld
- CPLD与电子CAD报告 VHDL中的并行语句、进程 信号、变量、顺序语句 分频器、计数器、译码器、状态机 数字钟综合设计-CPLD and VHDL electronic CAD report in parallel statement, the process signals, variables, sequential statements divider, counter, decoder, an integrated digital clock state machine des
count
- 能实现秒分频的计数器,调用元器件，用VHDL语言编写-To achieve second frequency division counter，Calls components, written in VHDL language
SyncounterFinal
- 在Xillinx ISE 平台上利用VHDL语言实现同步计数器，利用状态机实现，导入FPGA版点亮7段数码管并实现加、减计数功能。-The programme realizes a counter based on synchronous state machines, and it can be download to a FPGA chip.
counter9
- 运用VHDL输入方式设计一个0-9之间的减1计数器，完成程序的编译、综合、仿真测试，并给出仿真波形-Design using VHDL input between minus a 0-9 counter, complete compilation, synthesis, simulation, test procedures, and gives the simulation waveforms
adder_shifter_counter
- 用VHDL写的全加器，移位寄存器，和计数器，并有文档说明，非常详细。-Using VHDL write full adder, shift registers, and counters, and is documented in great detail.
practise
- FPGA实验板设计一个数字跑表。根据题目要求利用VHDL语言设计出一个系统，包括分频器，开关消抖，使能控制，计数器，锁存器，数据选择器及显示译码器。-FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, c
8bit-cpu
- VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计-VHDL realization 8 of cpu design
fenpin1s
- 计数器实现分频，将100M的机器频率分成1HZ。是基于VHDL实现的。-Counter to realize frequency division, the machine frequency of 100 m can be divided into 1 hz. IT s based on VHDL
count
- 基于vhdl语言设计实现的计数器程序，可实现模为10.12等等的计数器。-Vhdl language-based design and implementation of a counter, which enables the mold to 10.12 etc. counter.
shiyan2
- 含异步清0和同步时钟使能的加法计数器的设计，可以从0加到99，使用VHDL语言-Cleared containing asynchronous and synchronous clock enable the addition of counter design, added to 99 can range 0, the use of VHDL language
count_nixie
- 计数器加数码管译码，计数功能然后在数码管上显示，使用VHDL写成-counter encoder
cnt100
- 一百进制计数器，采用层次化设计，底层文件为十进制计数器，顶层文件原理图设计-the procedure is based on vhdl,it can count 100,and use top-down
8sfdsd
- 用VHDL实现的八位可逆计数器，可作为交流学习使用。-VHDL implementation with eight reversible counter can be used as the exchange of learning to use.
demo3-seg2_vhdl
- ep1c3-seg1_vhdl,７段数码管实验２：递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. 设计了一个4位十进制计数器，并用数码管显示当前计数值-ep1c3-seg1 vhdl, 7-segment LED Experiment 2: incrementally on four digital display counts up 0000-0001-> 0002 ...... ..9999 ... ...
divider
- 用VHDL程序实现数字电路里面的分频计数器的功能-Digital circuitry inside the program using VHDL-scale counter function
DTCNT9999
- 9999计数器，源代码用VHDL进行书写，设计中有计数模块，动态扫描模块，动态显示模块。书写规范，易于理解。-9999 counters, source code written in VHDL are, in the design of counting module, dynamic scanning module, dynamic display module.
cnt2
- 16位二进制计数器及设计代码其测试代码（vhdl）-16-bit binary counter and design codes and test code (vhdl)
sin
- 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
asynchronous-counter
- 4个触发器构成的异步计数器,采用VHDL语言描述-asynchronous counter