搜索资源列表
alu_simulation
- VHDL alu unit design and simulation with RAM, ROM, clock generator and 2 simple programs to execute.
RNG
- Random number Generator based in vhdl
2DPSK-linan
- 全数字2DPSK调制解调系统，为VHDL语言。包括512分频器，M序列发生器等。整个过程完成2DPSK的调制与解调。-The full the digital 2DPSK modem system for the VHDL language. Including the 512 divider, the M-sequence generator. The whole process is completed 2DPSK modulation and demodulation.
FPGAMusic
- 基于FPGA的乐曲发生器电路设计，并附有VHDL源码！-FPGA-based music generator circuit design with VHDL source code!
sinx
- 完整的正弦波频率产生，详细的源程序以及完整仿真，对学习vhdl及eda很有帮助，在modelsim中仿真-Complete sine wave frequency generator
XINHAO
- 简易的信号发生器常见波形的VHDL编写程序。-Common waveform signal generator VHDL programming. Common waveform signal generator VHDL programming.
EDA1
- 用VHDL编程实现序列信号发生器与检测器设计和数字钟设计-VHDL programming sequence signal generator and detector design and the design of the digital clock
weisuiji
- 伪随机码系统器件发生器 产生伪随机序列 使用VHDL 语言开发设计，编写长度不长，只有20多行-Pseudo-random code system device generator produces pseudo-random sequence using VHDL language development and design, write the length is long, only 20 more lines
xyy
- 基于FPGA的vhdl语言的波形发生器材料及工程代码-FPGA VHDL language-based waveform generator materials and engineering code
biyesheji
- 信号发生器的源代码，VHDL实现，带有ASK，FSK等功能-The signal generator source code, VHDL, with features such as ASK, FSK
singen
- 利用vhdl在quartusii中编写的正弦信号发生器，并在quartusii中进行了仿真-Using the VHDL in a QuartusII in the preparation of the sinusoidal signal generator, and makes simulation in QuartusII
RISC_CPU
- VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator,
fsk_tz
- vhdl实现FSK调制，本次毕业设计的数据速率 1.2kb/s，要求产生一个1.2kHz的正弦信号，对正弦信号每周期取100个采样点，因此要求产生3个时钟信号：1.2kHz（数据速率）、120kHz（产生1.2kHz正弦信号的输入时钟）、240kHz（产生2.4kHz正弦信号的输入时钟）。基准时钟已由一个外部时钟120MHz提供，要得到前面三种时钟，就需要首先设计一个模50的分频器产生240kHz信号，再设计一个二分频器，生产一个120kHz的信号，然后再前面的基础上再设计一个模100的分频器，
wave_gen
- VHDL编写的波形发生器，可以产生方波，并可自己调整所产生的波形占空比等-VHDL prepared by the waveform generator, can produce a square wave, and may adjust the waveform
UniformRNG
- A Uniform Random Number Generator in VHDL
VHDL_waveform_generator
- 多功能波形发生器VHDL编程与仿真，可以来学习啊-VHDL programming and simulation of multi-function waveform generator, you can learn it
m_seq
- 用VHDL代码编写的m序列发生器，包含发生器和测试用例模块-M sequence generator written in VHDL code, including the generator and the test case module
pmuxxplusii-vr
- 用VHDL开发的数字时时钟，可变宽度脉冲产生器 -VHDL development of digital clock, variable-width pulse generator
hang
- 用VHDL编写程序实现VGA彩条信号发生器 显示行彩条-VGA color bar signal generator display line color bar with VHDL programming
EP5_PWM_GENERATOR
- PWM信号发生器VHDL源程序+设计思路等等的内容-The contents of the PWM signal generator VHDL source+ design ideas, etc.