搜索资源列表
DDS
- DDS正弦波形发生器，VHDL语言描述！-DDS sine waveform generator, VHDL language descr iption!
sinout
- VHDL的正弦信号发生器设计，功能大家都知道了！！就不用说了呀-VHDL design of the sinusoidal signal generator, function as we all know it! ! Needless to say it! !
FPGA-BOXING
- 基于FPGA的波形发生器，通过QUARTUS ii 软件，用VHDL语言编写的波形发生器-FPGA-based waveform generator, QUARTUS ii software waveform generator using VHDL language
DDS
- 利用现场可编程逻辑门阵列FPGA实现直接数字频率合成（DDS）的原理，以及以DDS为核心的信号发生器。探讨DDS技术在FPGA中 的实现方法，提出采用ALTERA公司的FLEX系列FPGA芯片FLEX10K进行直接数字频率合成的VHDL源程序。-The use of field-programmable gate array FPGA to realize the principle of the direct digital frequency synthesis (DDS) DDS as t
xinhao
- VHDL语言的波形发生器的设计过程和使用-The design process and use of the VHDL language waveform generator
lfsr
- the LFSR is coded in VHDL, using a structural descr iption, which is instantiated as a separate component in the top-level design. Then we can get a random number by a pseudorandom number generator based on a linear feedback shift register (LFS
clock-divider
- clock generator vhdl code
DDSVHDLCODE
- 本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。-I collected multiple VHDL language of sine wave generator SPWM program.
sin
- vhdl语言写的基于rom的正弦波发生器，包含代码和仿真图-VHDL language used to write rom-based sine wave generator contains code and simulation Figure
vga_timing_vhdl
- Timing generator for displaying graphics on a VGA screen in VHDL
xinhao
- 简易信号发生器，可输出三种波形，递增锯齿波发生器模块，正弦波发生器模块，方波发生器模块，波形选择器模块，vhdl-Simple signal generator can output three waveforms, incremental sawtooth generator module, the sine wave generator module, a square wave generator module, waveform selector module, vhdl
cos-fangshengqi
- 正弦波发生器的产生，让你有VHDL设计一个正弦波发生器-The generation of the sine wave generator, VHDL design of a sine wave generator
test_parity
- parity generator in vhdl
doxygen_manual-1.8.3
- Doxygen是一种开源跨平台的，以类似JavaDoc风格描述的文档系统，完全支持C、C++、Java、Objective-C和IDL语言，部分支持PHP、C#。注释的语法与Qt-Doc、KDoc和JavaDoc兼容。Doxgen可以从一套归档源文件开始，生成HTML格式的在线类浏览器，或离线的LATEX、RTF参考手册。-a code document generator tool for * C/C++ * Java * Objective-C * Python * ID
ca_prng_latest.tar
- Pseudo random noise generator/ implemented in VHDL/Verilog
EXP5_PWM_GENERATOR
- 用FPGA设计的一种pwm波形生成器，语言为VHDL-FPGA design a pwm waveform generator, language VHDL
lab_2
- VHDL 实现M序列发生器 附带测试与限定文件-M-sequence generator VHDL incidental test with limited file
hanshufashengqi
- 设计一个函数发生器，用VHDL语言实现。可以实现正弦、余弦等多种函数的波形-Design a function generator using VHDL. You can achieve a variety of functions such as sine, cosine waveform
DDS
- DDS信号发生器设计程序,内含各种増频，转码，变形的VHDL语言-DDS signal generator design process, containing a variety of Increase frequency, transcoding, the deformation of the VHDL language
coregen_overview
- core generator vhdl book