搜索资源列表
Signal3
- ISE设计的三角波发生器VHDL实现及报告-ISE Design of the triangular wave generator VHDL implementation and reporting.
SHIYAN
- VHDL多个小实验，包括加法器，AD变换，状态机、波形发生器等-VHDL several small experiment includes an adder, AD conversion, the state machine, the waveform generator
Golden
- VHDL编写的golden码，发生器，代码注释详细，简单易懂，便于学习-VHDL, golden code generator, code notes detailed, easy to understand, easy to learn
Mxulie
- VHDL语言编写，利用FPGA实现的M序列发生器-VHDL language, FPGA realization of the M sequence generator
mvhdl
- m序列发生器vhdl语言quartus2-m sequence generator vhdl language quartus2
sqr
- VHDL CODE FOR SQUARE WAVE GENERATOR
SineGen
- Basic VHDL code to create a sine wave generator for an FPGA board.
key2
- FPGA单片机 vhdl编程正弦波信号发生器 加2个按键控制频率加减-FPGA Microcontroller vhdl programming sine wave signal generator plus two buttons control the frequency of addition and subtraction
wave_freq
- 在VHDL/verilog环境下产生可调频率的波形，如三角波，方波，矩形波，同时支持计数功能，供参考-Adjustable frequency waveform generator in VHDL/verilog environment, such as triangle wave, square wave, rectangular wave, while supporting the counting function, for reference
12
- 在vhdl语言的环境下，自己设计正弦信号发生器，其中也包含一小段c语言程序-In vhdl language environment of their own design sinusoidal signal generator, which also contains a small c language program
Waveform-generation-program
- 基于VHDL语言的波形发生器编程设计，能够实现常用波形的产生。-Waveform generator design based on VHDL programming, to achieve common waveform generated.
DDS
- 本设计基于数字频率合成技术,采用正弦查找表实现波形产生.直接数字频率合成技术（DDS）是一种先进的电路结构，能在全数字下对输出信号频率进行精确而快速的控制，DDS技术还在解决输出信号频率增量选择方面具有很好的应用，DDS所产生的信号具有频率分辨率高、频率切换速度快、频率切换时相位连续、输出相位噪声低和可以产生任意波形等诸多优点。 文中介绍了DDS的基本原理，对DDS的质谱及其散杂抑制进行了分析。程序设计采用超高速硬件描述语言VHDL描述DDS,在此基础上设计了正弦波、三角波、方波等信号发生器，。
pwm_ok_PWM
- 用VHDL实现占空比任意可调的PWM产生器。（程序逐行注释），有仿真图。PWM,即Pulse-Width Modulation 脉宽调制，常用于电机的控制中。-Using VHDL adjustable duty cycle of PWM generator. (Progressive program notes), a simulation map. PWM, i.e. Pulse-Width Modulation PWM, used to control the motor.
wave111
- 基于VHDL的正弦波信号发生器，频率可以调节-Sine wave signal generator, the frequency can be adjusted
key2
- FPGA单片机 vhdl编程正弦波信号发生器 加2个按键控制频率加减-FPGA Microcontroller vhdl programming sine wave signal generator plus two buttons control the frequency of addition and subtraction
spi
- 基于system generator的SPI协议的设计，能自动转换成verilog或VHDL语言-Based on the system of the generator SPI protocol design
test_clkgen
- Test Clock Generator. You can learn how to implement test clock generator in VHDL
1
- 信号发生器VHDL实现,实现一种信号的产生-Signal generator VHDL implementation to achieve produce a signal
Lab1~3
- 此為VHDL之暫存器、栓鎖器、三態匣、計數與除頻電路以及時脈產生電路-This is a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit
SINGT
- 基于FPGA的用VHdl硬件编程语言实现的正弦波发生器。-FPGA-based hardware programming language with VHdl sine wave generator.