搜索资源列表
mima
- 基于FPGA的电子密码锁控制电路的设计，包涵源代码和密码锁的整体组装设计原理图-FPGA-based electronic code lock control circuit design, includes source code and password lock schematic design of the overall assembly
vhdljiaocheng
- 献给有志于学好FPGA软件的人。这是一本VHDL的电子版教程，写的很详细，希望对各位有所帮助。-FPGA dedicated to those who want to learn software. This is an electronic version of vhdl tutorial, written in great detail, and they hope to help you.
CRC32
- CRC32 Vhdl component
yetert
- This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).
4559939-VGA-Video-Signal-Generation
- source code VGA for Xilinx FPGA Spartan 3E
leon3
- 这个一个基于amba总线的leon3处理器的vhdl语言程序描述，学习fpga总线开发的请看-The amba bus-based processor vhdl language leon3 procedures described in the study developed fpga see bus
FPGAModele
- 基于FPGA的数据采集模块的设计，通过该文章能让读者学会很多-FPGA-based design of data acquisition module, through which readers can learn to a lot of articles
rafal2
- VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
RSandfpgadesign
- 详细介绍了RS编解码背景以及原理，同时给出了FPGA实现方案-Described in detail the background of RS codecs as well as the principles of the FPGA at the same time give the realization of the program
VGAWorm
- VGA game implemented on FPGA
ZX
- 本系统以51单片机及FPGA为控制核心，由正弦信号发生模块、功率放大模块、调幅（AM）、调频（FM）模块、数字键控（ASK，PSK）模块以及测试信号发生模块组成-The system of 51 single-chip and FPGA for the control of the core module by the sinusoidal signal, power amplifier module, AM (AM), frequency modulation (FM) module, dig
vhdl
- fpga的时钟讲解，vhdl的，源代码，可以测试-fpga on the clock, vhdl, and source code, to test
reed
- this the completedocumentation and code about reed solomon logic implemented on fpga in verilog.-this is the completedocumentation and code about reed solomon logic implemented on fpga in verilog.
MQdecoder
- Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA， Verilog HDL
digitaloscilloscope
- This digital oscilloscope takes a MCU and FPGA as the core. We made emphases on the choice of the sampling methods and the implement of equivalent sampling as a result, our design not only has the real-time sampling mode but also can reach the highes
ddr2_hamdec64
- VHDL实现的64bit海明码解码模块。 可适用于 Xilinx FPGA, Altera FPGA。-VHDL Implement 64bit Hamming Code （decode）
ddr2_hamenc64
- VHDL实现的64bit海明码编码模块。 可适用于 Xilinx FPGA, Altera FPGA。-VHDL Implement 64 bit Hamming Code (encode)
are_you_pld_metastable
- cypresss出品的，讲述FPGA 亚稳态 问题的好资料。阐述清晰到位。 -Metastable problem solution by Cypresss
A_study_about_FPGA_based_digital_filters
- Digital hilbert transformers for FPGA-based phase-locked loops
spi_master_control
- VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website