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electronic-clock
- 数字电子钟是数字电路中的一个经典学习内容。我们选用电子钟作为最后结课项目的目的,是为了学习verilog语言、FPGA的基本知识、由顶层至底层的设计思路。-VHDL source code for electronic clock design to share
17-Clock
- 这是一个成功的电子钟VHDL和Verilog源代码,已在DH-33001开发板上调试成功。-This is a successful electronic clock VHDL and Verilog source code, in the DH-33 001 development board debugging.
SOPC_watch
- 基于ALtrafpga的niosii内核verilog语言实现的可编程电子钟,需要外接lcd屏幕-Programmable electronic clock, based on the the ALtrafpga the kernel niosii verilog language to achieve an external lcd screen
VVerrilogclloe
- 用VERILOG语言开发的电子钟程序源码码.是用GW48教学实验箱仿真 -Electronic clock with VERILOG language program source code. GW48 teaching experiment box simulation
clock_FPGA_verilog
- 简易电子钟的设计(verilog HDL)-Simple design of the electronic clock (verilog HDL)
clock
- Quartus II软件设计数字电子钟,使用verilog语言编写各个 模块生成symbol files,再用原理图方式制作顶层文件。 完成的功能有:能够显示时、分、秒;具有清零,调节分钟的功能; 具有整点报时功能,声响电路发出叫声; -failed to translate
clock
- 用verilog编写的电子钟,里面用各个模块实现,使七段数码管上显示小时和分钟,读秒用数码管的点表示-Using verilog electronic clock, with each module inside, so the seven-segment digital display hours and minutes on the tube, with the point of a digital countdown said tube
dianzizhong
- 使用Verilog语言编写的电子钟,课堂小实验,经过测试可用。-Electronic clock, with Verilog language classroom experiments, after testing is available.
try1
- 电子钟设计,verilog语言编写,拥有数秒和计时两个主要功能-4 bit digital clock, might function as a stopwatch
baseonFPGAclock
- 用verilogHDL语言写的基于FPGA的电子钟。里面包含闹钟、秒表、日历、时间设置等功能,可用LCD显示-verilog language, implemented on the FPGA alarm clock, calendar, time display, stopwatch in one of the electronic clock and calendar. Can be displayed on LCD