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lcd1602_drive
- 简介 程序是用quartus.exe 开发的verilog 源程序 实现了lcd1602的驱动-About quartus.exe development program is implemented lcd1602 verilog source driver
gradtobin
- 格雷码转二进制的程序(verilog),经过验证quartus、8.1-grad to binary
liangzhu
- 用Verilog语言编写梁祝歌曲,用quartus编译文件-Butterfly Lovers with Verilog language songs, compiled files with quartus
20104169105873879
- 主要功能:pci9054芯片本地总线控制示例程序,可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断,产生1,2,3等递增数据,配合pci9054驱动和应用程序完成数据传输 2.说明:文件夹内是Quartus 9.0的工程文件,使用Verilog语言,使用器件是Cyclone2,应用于其他FPGA时,直接调整管脚即可。-Main features: pci9054 local bus control chip sample program can be used for pci driv
2011-03-09
- 基于quartus II cycloneII verilog分频器-Divider based on quartus II cycloneII verilog
mcbsp_to_sci
- 自己写的 mcbsp 转 sci 和 sci转mcbsp 的verilog的程序,欢迎大家 指点,开发环境是Quartus II。-Write your own mcbsp turn sci and sci turn mcbsp the verilog program, we welcome the pointing
spi
- 用verilog实现的 SPI 源码,可以直接通过Quartus运行-SPI with verilog source implementation can be run directly through the Quartus ~ ~
rise-or-fall-detect
- 上升沿、下降沿检测代码,开发语言是verilog HDL,希望对大家有所帮助-rise or fall detect of information and the tool is the software Quartus and the landuage is vrilog HDLthank you for using it hope it will benifit for you
hm
- 汉明编码和解码的硬件描述语言(verilog),其被编解码的数据为M序列。 建议运行软件为Quartus.-failed to translate
VGA_char
- Verilog语言描述的VGA显示实验,主要目的是在屏幕上显示不同的字符,Quartus 10 中编译通过。-Verilog language descr iption of the VGA display experiment, the main purpose is to display different characters on the screen, Quartus 10 in the compile.
UART_FIFO
- Verilog 语言描述,基于FIFO设计的UART。Quartus 10中编译通过-Verilog language descr iption, based on the design of the UART FIFO
10-binary-counter
- 使用verilog实现10进制计数器功能,可以实现Quartus仿真,含任意进制计数器程序-10 binary counter using verilog implementation function, can realize Quartus simulation program with an arbitrary binary counter
final
- This Source is Verilog Coding. Made in Altera Quartus 9.0 Service Pack 3. Important, I know not used board.
sdr
- 全数字OQPSK解调算法的研究及FPGA实现 论文介绍了OQPSK全数字接收解调原理和基于 软件无线电设计思想的全数字接收机的基本结构,详细阐述了当今OQPSK数字 解调中载波频率同步、载波相位同步、时钟同步和数据帧同步的一些常用算法, 并选择了相应算法构建了三种系统级的实现方案。通过MATLAB对解调方案的 仿真和性能分析,确定了FPGA中的系统实现方案。在此基础上,本文采用Verilog HDL硬件描述语言在Altera公司的QuartusⅡ开发平台上设计
calc
- 计算器源代码,Quartus II Verilog-Calculator source code, Quartus II Verilog
fun
- 用函数对信号进行处理。Quartus II Verilog-With the signal processing functions. Quartus II Verilog
quartus_error
- 关于Verilog HDL语言的集成开发环境quartus 的一些常见的错误分析-On the Verilog HDL language integrated development environment quartus some of the common error analysis
hgfdg
- Quartus? II 相关的语言 详细介绍了VHDL verilog软件开发过程-Quartus ? II related language detailed introduces the verilog VHDL software development process
sixiangzaibosheji
- 本代码采用Altera公司的FPGA为主控芯片,以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz,输出四路频率为70MHz的四相序正弦载波(相位分别为0°、90°、180°、270°)的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真,验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70M
t12
- quartus 9.0的工程,verilog编写,步进电机控制,可以调速和控制位置.可综合。-Quartus project files are included in RAR file. It s written in verilog HDL ,and the purpose is to control both the speed and position of Stepper motor。And project passed synthesis.