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Experiment04
- 浮点数的除法器的Verilog 源代码,使用Quartus II开发环境编写,塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
13_flash
- 用于读写8位数据口的FLASH芯片,使用Quartus II开发,Verilog文件-used to read or write the 8bit Flash Chip,developed by Quartus with Verilog language
23_lan
- Lan芯片ENC28J60的驱动程序,Quartus II开发,Verilog编写-the driver for a Lan Chip ENC28J60,developed by Quartus II using Verilog
88RISC-CPU
- cpu设计能在quartus上运行 用verilog语言-a cpu program use verilog on quartus
16QAM
- 使用verilog编写的16QAM调制解调代码,可用于quartus和ISE,因为不包含FIR,只能用于仿真,不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
EJEMPLOS-(1)
- quartus ii introduction to verilog
clk_div_3
- 利用Verilog语言实现3分频,在Quartus中调试通过!-Use Verilog language divide by 3, in Quartus debugging through!
uart_async
- RS232串口通信代码,采用verilog HDL实现,在quartus上仿真通过并下载到fpga平台功能验证-RS232 CODE
ASS2_bench
- Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II Quartus-Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II QuartusII
EDA
- 我的EDA课程设计 Verilog HDL 自动售票机的实现 ·设计目标: 本设计完成基于Verilog HDL的自动售票系统,综合软件用Quartus II8.1。 本自动售票系统可以完成1元、2元、3元、4元四种票的自动售出,货币种类可以是1元、5元、10元、50元、100元,能自动找零和显示 ·总体设计: 共有四个主要模块和一个顶层模块:四个模块分别是主控模块、统计模块、出票模块和找零模块;顶层模块负责各模块间的连接,组成一个可用的自动售票系统。-My EDA
stopwatch
- FPGA程序,verilog HDL语言编写的秒表程序,使用quartus II 13.0 开发,初学verilog HDL的同学可以参考下-FPGA procedures, verilog HDL language stopwatch program, developed using quartus II 13.0, verilog HDL beginner students can refer
FPGA_Uart
- FPGA程序,verilog HDL语言编写,包含AD转换和串口发送程序,由于AD芯片种类繁多时序迥异,故主要参考串口发送程序。本程序使用quartus ii 13.0 编写。-FPGA procedures, verilog HDL language, includes an AD converter and serial transmission program, since a wide range of AD chip timing are different, so the main
FPGA_cymometer
- FPGA程序,verilog HDL语言编写,提供了一种频率计的实现方式,开发环境为Quartus ii 13.0,初学verilog HDL语言的同学可以参考下-FPGA procedures, verilog HDL language, provides a way to achieve a frequency meter, development environment for Quartus ii 13.0, beginner verilog HDL language students
yima
- Verilog语言描述38译码器功能,适用于ISE或者quartus软件-Verilog language descr iption 38 decoder function for ISE or quartus software
fifo2
- 异步fifo 先进先出 用于缓冲数据,用verilog HDL所写,在quartus II中测试通过,modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
music
- 在FPGA平台上Verilog实现简易电子琴功能,可直接用Quartus下载到板上运行。-A simple electronic organ function
adder4
- 使用层次化建模的方法再quartus下实现的4位全加器。包括半加器,一位全加器和四位全加器,并进行了仿真。-This file is used for learners to learn verilog.
HL-340_xp
- quartus verilog FPGA/cpld 例程 verilog简单例程-quartus verilog FPGA/cpld verilog simple routine routines
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器,用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
FPGA_CRC
- 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码,verilog HDL源代码,并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟,仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source cod