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xuexidds
- 利用quartus平台使用verilog语言实现直接数字频率合成-Use quartus platform verilog language Direct Digital Synthesis
ARINC_429
- FPGA实现ARINC429协议,利用verilog HDL做了完整的ARINC429通信收发协议,EDA开发平台为quartus ii9.1。-FPGA implementation ARINC429 protocol using verilog HDL to do a complete ARINC429 communication transceiver protocol, EDA development platform quartus ii9.1.
zsy_422_20160911_backup
- RS422协议芯片OX16C950底层驱动程序,Verilog语言编写,Quartus ii 15.0开发,可实现数据收发,用串口调试助手可以观察。-RS422 protocol chip OX16C950 low-level driver, Verilog language, Quartus ii 15.0 development, can achieve data transceiver, with the serial debugging assistant can be observed
lan91c111
- MAC芯片LAN91C111驱动源码,quartus开发环境,Verilog HDL开发语言。自己编写调试通过。对FPGA控制MAC开发者非常有用。-MAC chip LAN91C111 driver source code, quartus development environment, Verilog HDL development language. Write debugging through their own. Very useful for FPGA control MAC d
pic10
- 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码,当然有一些模块是在quartus中直接编辑波形测试的,所以没有响应的测试脚本文件。 tri_state_port的测试还未完成,test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档: PIC10_RISC_Design.pdf:原文(verilog代码基本都来自原文,对一部分进行了改进),这篇文章写
20161122_ff
- MD5认证部分的第一轮中包含F函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-MD5 authentication part of the first round contains an F function of the operation of the FPGA implementation of the source code, using Verilog, integrated in the Quartus II
20161122_gg
- MD5认证部分的第二轮中包含G函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-FPGA contains one operation in the second round of the G function MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II
20161203_hh
- MD5认证部分的第三轮中包含H函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-FPGA third round included H functions in one operation MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II
20161203_ii
- MD5认证部分的第四轮中包含I函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-The fourth round MD5 authentication section contains FPGA one operation I Functions of the source code, using Verilog, synthesis in Quartus II
freq_100M
- 在FPGA平台上,verilog,频率测量,已调试,可在quartus上打开。-On the FPGA platform, verilog, frequency measurement, debugged, can be opened on quartus.
m-Sequence
- FPGA,verilog,输出M序列,已调试成功,可直接在Quartus上打开。-FPGA, verilog, output M sequence, has been successfully debugged, can be opened directly on the Quartus.
zhixinkeji
- 北京至芯科技FPGA的学习资料,从备战Quartus II安装到IIC通信协议,每一章都有Verilog代码并且可以实现仿真程序,非常好用,讲的很详细-Beijing Science and Technology FPGA to the core learning materials, preparing to install Quartus II IIC communication protocol, each chapter Verilog code and can achieve sim
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程,可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元,外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008),可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
EDA
- 熟悉QuartusⅡ的Verilog HDL文本设计流程全过程,学习计数器的设计、仿真和硬件测试。-Familiar with Quartus II Verilog HDL text design process, learning counter design, simulation and hardware testing.
UART
- 用Verilog实现的全局异步接收发送机,在quartus平台测试成功。(Use Verilog implementation of global asynchronous receive transmitter in quartus platform test successfully)
4x4 Keypad
- 用Verilog实现的4*4键盘扫码程序,在quartus平台实现。(Use Verilog implementation of 4 * 4 keyboard scan code program, realized in quartus platform.)
LCD1602
- 用Verilog实现的液晶显示屏程序,在quartus平台上测试成功。(Use Verilog implementation of LCD display program, on quartus platform test successfully.)
PWM
- 用Verilog实现的脉冲宽度调制程序,在quartus平台上测试成功。(Using Verilog implementation of pulse width modulation, in quartus platform test successfully.)
CCD_drive
- TCD1304 CCD 驱动 AD转 USB2.0传输(This code based on verilog language, worked on EP1C3T144 FPGA chip, developed on Quartus II 12.0 . The ccd's data transformed by USB2.0 after amplified and AD confromed.)
chuankou
- 此文件是一个串口verilog程序,一次传输一个字节,使用quartus编写(This is a program that is written in Verilog language ,It is a Serial program ,You can transfer and return a byte data.)