搜索资源列表
sdram_singale_word
- 使用verilog驱动的sdram单字节读写,可以学习一下sdram最基本的功能,学习sdram参考程序。-Use sdram verilog-driven single-byte read and write, you can learn the most basic functions sdram, sdram reference learning program.
sdram_mdl
- 基于SDRAM的读写调试试验,使用verilog语言编写,经过调试。-SDRAM-based literacy commissioning tests, using verilog language, through debugging.
SDRAM_interface
- SDRAM verilog 代码,已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a re
sdram_5
- SDRAM的verilog描述,包含顶层设计,测试平台代码,精确描述-SDRAM is verilog descr iption, including top-level design, testbench code, an accurate descr iption of
SDRAM_96M
- 基于FPGA的SDRAM串口实验,verilog语言写的,附件里是做实验的工程,连上串口,下进去就有数据了,波特率9600,一个停止位,SDRAM时钟是96MHz,数据时FPGA自动产生的,正确输出结果是00到FF递增一,再循环。这个工程警告比较少,基本是故意为之的警告,时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even o
sdram_top
- 使用FPGA实现SDRAM逻辑控制器,适用于各种型号的FPGA-SDRAM control by verilog
S27_SDRAM_IP
- SDRAM 驱动读写demo,用verilog写的上板测试过-SDRAM verilog
ALTERA_FPGA_SDRAM
- 使用ALTERA的FPGA控制SDRAM的verilog程序-Use ALTERA s FPGA to control SDRAM s verilog program
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法,(Verilog HDL)设计所需的模块有: (1)带PLL的全局时钟管理模块 system_ctrl_pll.v (2)OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig (3)OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 (4)SDRAM数据交互控制器Sdram_Control_2Port (5)VGA时序
DDR3 SDRAM Verilog Model
- ddr3的逻辑带么参考,有需要的可以看一下。。。。。。。。。(ddr3 ssscoede code code code)
4NandFlash
- 控制器顶层,以及实现功能模块简单的snandflash_top_ctrler(Simple nand_flash_top_ctrler)
C5G_SRAM_RTL_Test
- 官网c5板子的SRAM工程,可以直接一直使用。(The SRAM project of official website C5 board can be used directly)