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经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。,Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
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CIC梳状滤波器verilog源码，包括积分器，下抽级以及梳状滤波器三个部分。,CIC comb filter verilog source code, including the integrator, under the pump, as well as comb filter class is in three parts.
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1 fpga驱动lcd液晶12864的verilog源程序
(显示英文，可以在源程序中直接修改成自己想要显示的英文)
2 引脚配置完成，程序已经测试，完全好用
3 使用的FPGA芯片是altera的max2EP2C5T1-1 fpga driver' s verilog source code 12864 lcd LCD (display in English, you can directly modify the source program into what you w
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该压缩包包括NAND FLASH（美光）的FPGA控制器的原理及VHDL源码，非常具有参考价值。-The archive includes NAND FLASH (Micron) the principle of the FPGA and VHDL source code control, very valuable reference.
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HDMI interface verilog code and specificaiton paper
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两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
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这是电话计费器的Verilog源程序，已经编译通过，可以直接使用-This is a call accounting device Verilog source code, has been compiled by, can be used directly
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FPGA开发板上的VerilogHDL编写的SRAM读写试验程序, 包括介绍文档, Verilog源码, 在Quartus II 8.1环境下测试通过-FPGA development board SRAM VerilogHDL prepared to read and write test procedures, including the descr iption document, Verilog source code, the Quartus II 8.1 environment te
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SST39VF1601.c
sst39vf1601源代码
-SST39VF1601.csst39vf1601 source code
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用verilog写的8B10B编码源代码。似乎有点难度来理解。这里并未使用case语句，而是完全的用的组合逻辑化简-Use verilog write 8B10B encoding source code. Seems difficulty understood.
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32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
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乘法器
verilog CPLD
EPM1270
源代码-Multiplier verilog CPLDEPM1270 source code
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关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
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H.264编码的verilog源代码，希望各位研究研究，定会有收获的-H. 264 coding verilog source code, how to understand, hope that you study
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Verilog DLL sOURCE CODE
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用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
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ARM9的开发源代码，全套，很难得。
现全部共享。-ARM9 development of source code, a full set, it is difficult to get. Are all shared.
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基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
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SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
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or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog descr iption of the risc cpu realize, cpu source code analysis and chip design source book
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