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使用SNTP协议连接GPS服务器,并同步本地时钟,是一个简单的使用例子-SNTP agreement linking the use of GPS server, and the local clock synchronization is a simple example of the use of
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因特网时钟校对程序,Visual C++实现,很好的例子。-Internet clock synchronization procedures, Visual C + +, a very good example.
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可以监测cpu时钟周期,用于分布式系统需要时钟同步的场合,该程序包含源代码-can monitor CPU clock cycle, the need for distributed system clock synchronization occasions, the program includes source code
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2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码,实现后端采样同步时钟-E Electronic Design Contest 2011 problem " simple digital signal transmission analyzer" verilog source code sample to achieve the back-end clock synchronization
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使用VERILOG开发时钟同步算法,能够从数据信号中提取时钟信息,-Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,
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本文件是在ALTERA公司的QUARTUS下VHDL+原理图编写的时钟同步逻辑-This document is in the company' s QUARTUS ALTERA under VHDL+ schematic written clock synchronization logic
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基于verilog的鉴相器设计,鉴相器是锁相环的一部分,功能是检测两个时钟是否同步-The phase detector based on verilog design, PLL phase detector is part of function is to test whether the two clock synchronization
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用RMI实现在JAVA环境下服务器与客户端的时钟同步。-RMI implementation using JAVA environment in the server and the client clock synchronization.
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IEEE 1588 精密时钟同步的源代码-the code of IEEE 1588 Precision clock synchronization Protocol
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java 实现的同步时钟,通过此功能可以对网络中的时钟进行同步操作。-java achieve synchronization clock, this feature can network clock synchronization.
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用FLASH和JAVA制作一个实时同步的时钟-With FLASH and JAVA to produce a real-time clock synchronization
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使用FPGA/CPLD设置语音AD、DA转换芯片AIC23,FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz,SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/
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生成一个带表盘和时分秒针的指针式时钟,并于电脑的时间同步-Generate a dial with second hand and the pointer around the clock, and computer time synchronization
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用VHDL 设计的单时钟同步十进制可逆计数器的设计-VHDL design using a single clock synchronization decimal CNTR Design
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用vc实现一个和系统时间同步的时钟,实现了同步刷新功能和基本的画图功能-With vc the realization of a time synchronization and system clock to achieve synchronization of the refresh function and the basic drawing functions
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使用FLASH MX制作的石英钟,与系统时钟同步-FLASH MX produced by the use of quartz, with the system clock synchronization
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显示时钟,从系统中读取,指针时钟,与系统显示的时间同步-Display clock, reading from the system, the clock pointer, and the system shows the time synchronization
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FIFO以及跨时钟域的同步问题。
FIFO有分离的地址总线和用以读写数据的数据通道,以及指示堆栈状态(满、将满等)的状态线。-FIFO as well as cross-clock domain synchronization. FIFO have separate address bus and read and write data to the data channel, as well as the instructions state stack (full, will be fu
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锁相环是一种反馈电路,其作用是使得电路上的时钟和某一外部时钟的相位同步。PLL通过比较外部信号的相位和由压控晶振(VCXO)的相位来实现同步的,在比较的过程中,锁相环电路会不断根据外部信号的相位来调整本地晶振的时钟相位,直到两个信号的相位同步。-PLL is a feedback circuit, and its role is to make the clock circuit and a phase of external clock synchronization. PLL signal
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这是介绍IEEE1588网络时钟同步的资料,非常有用,可以用在仪器设备同步,通信等行业.-This is to introduce the IEEE1588 network clock synchronization information, very useful synchronization can be used in equipment, communication and other industries.
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