搜索资源列表
counter
- 59计时器 希望用的着的朋友们能够有用的价值，在此奉上。-59 counter
Score-counter
- 高质量的，应用VisualC++编辑的分数计数器-Score counter is based on Visual C++
counter
- 应用FPGA中VHDL语言编写计数器程序-Application of VHDL language preparation FPGA counter program
Counter
- 用Java编写的计算器，图形界面，适合学生学习-A counter， using java，swing
counter
- VHDL 脉冲输入15进制输出计数器 计数器是实际中最为实用的时序电路模块之一-VHDL pulse input the counter of the output of the 15 hexadecimal counter the one of the of yes one of the the actual in the the most practical timing circuit module
Digital-pulse-counter-design
- 《数字脉搏计数器设计》，电子设计的文档！-Digital pulse counter design, electronic design document!
Verilog16-bit-counter-design
- Verilog16位计数器设计,可实现简单的16位数的计算。-Verilog16 bit counter design, simple 16-digit calculation.
counter
- 利用verilog开发的计数器程序，比较基本，包含完整的工程-Use of the the verilog development of counter program, more basic, including complete engineering
frequency-counter
- 这是使用VHDL语言编写的频率计数器源码。包含了各个模块以及主函数。-This is the source of the frequency counter using VHDL language. Contains various modules and the main function.
counter-interrupt-8-timer-04s
- 单片机源程序（keilC语言）---计数器中断8次定时04s件，不需编程，但仅是对霍尔传感器测速应用的验证。-SCM source (keilC language)--- counter interrupt 8 timer 04s
Counter-and-digital-tube-display
- 本文十、十二、十六，、六十进制计数器各一个，然后通过数据扫描分时模块与译码器模块在五个数码管上显示计数过程，六十进制计数器高、地位在不同数码管上显示。之后对程序进行调试和运行及仿真，仿真结果符合设计要求时使用JTAG下载到可编程器件中实现软、硬件结合。-This article ten, 12, 16, and six decimal counter counting process, six decimal counter, the status of digital tube displa
lcd-counter
- lcd counter wih memory and poush up and doawn
Mode-variable-counter-vhdl
- 模可变计数器 vhdl实现 quartus编译通过-Mode variable counter vhdl achieve quartus compiled by
JAVA-language-writing-counter
- JAVA语言编写计数器 -JAVA language writing counter
8-Bit-Up-Counter-With-Load
- 8位计数器，能实现加减计数，经过ise 测试仿真了。符合逻辑-8-bit counter, plus or minus count after ise test simulation. Logical
Divide-by-2-Counter
- 2分频，通过计数器实现，很实用的，可以作为时钟驱动。-Divide by the counter to achieve very practical, can be used as clock driver.
1100--counter
- cc1100或者cc1101在51处理器下的无线计数器keil程序-cc1100 or cc1101 51 processor, wireless counter keil program
COUNTER.ZIP
- 4 bit counter example for CHDL beginners
counter
- 用4个T触发器组成16位的计数器，FPGA实验ALTER DE2开发板自带光盘的案例程序解析-Four T flip-flop 16 of the counter, the case of FPGA experiment ALTER DE2 development board comes with CD-ROM program parse
counter
- 用vhdl语言，在QuartusII下，时序逻辑电路设计（带置位的异步可逆（加1或减1）6进制计数器）-With vhdl language, in QuartusII under sequential logic circuit design (set asynchronous reversible (plus or minus) hexa counter)