搜索资源列表
Structural-UpDown-Counter
- Structural UpDown Counter
timer-and-counter
- timer and counter by asm
counter
- push button counter, push 1 count 100, push 2 count 200, push 3 count 3-push button counter, push 1 count 100, push 2 count 200, push 3 count 300
Timer--Counter
- 用定时/计数器1控制LED灯闪烁 亮0.1s，灭0.9s，模拟路障灯的工作-With Timer/Counter 1 control LED lights flashing lights 0.1s, off 0.9s, analog barricade lights work
Up-counter-89s52
- AT89s52 based up counter 3 digit led 7 segment, protius simulation file include,asm code and hex code include,sw press for counter up.
6bit-Display-Counter
- 利用AT89S51单片机的T0、T1的定时计数器功能，来完成对输入的信号进行频率计数，计数的频率结果通过8位动态数码管显示出来。要求能够对0－250KHZ的信号频率进行准确计数，计数误差不超过±1HZ。-Using AT89S51 microcontroller T0, T1 timer counter function, to complete the input signal frequency count, counting the frequency of results through
Up-Counter
- 基于Quartus软件实现加法计数器，可以通过FPGA硬件系统来观测结果-Quartus software implementation based on adding counter, FPGA hardware system through observations
6-bit-Frequency-Counter
- 6位频率计数器，基于51单片机，亲测可用，请仔细阅读-6 frequency counter, based on 51 single, pro-test is available, please read
counter-00-99
- Counter 0 to 99 test on Digilend Basis2
counter
- 计算器的verilog语言程序代码。能实现加、减、乘、除运算。-verilog language of counter。it can achiev plus o, minus, multiplication and addition operations
counter
- This a VHDL file for 10 bit counter-This is a VHDL file for 10 bit counter
Counter
- Counter in VHDL using Xilinx ISE
Counter
- 点钞机----点钞机技术原理与系统设计资料-Counter---- Counter technical principles and system design information
php_anti-refresh-Web-counter-
- 用php制作 防刷新网页访问计数器,可防止刷新产生的计数.计数准确,精心挑选的style,美观大方,精巧实用-Produced anti-refresh with php web access counter , prevent refresh resulting count count is accurate, carefully selected style, elegant, sophisticated and practical
51timer-and-counter
- 1.定时器的基本驱动示例，定时器工作于方式1，下载程序后，隔三秒钟，第一个发光二极管被点亮；2.本程序提供一些常用定时器计时的具体参数。用的是定时器0工作于方式1。且只针对11.0592MHz的晶振。3.本程序为计数器的基本驱动示例，计数器工作于方式1。对按键S2按下的次数进行计数，当计数记到3时，第一个发光二极管被点亮。4“滴滴”声的产生5. 59秒计时器（利用定时器延时，查询法）6. 59秒计时器（利用定时器延时，中断法）7 59秒计时器（利用软件延时）-1 Timer basic driv
Counter
- 用VHDL设计具有清除端、使能端，计数范围为0-999的计数器设计。输出为8421BCD码-VHDL design with a clear end to enable the end, the design for the counter counting range 0-999. 8421BCD code output
Counter
- 计数器，低电平触发计数。采用AT89C52，驱动数码管显示。 使用12M晶振。-Counter, low trigger count. Using AT89C52, digital tube display driver. Use 12M crystal.
Binary-counter-experiment
- 利用NI ELVIS平台搭建电路，运用Labview编程，设计一个二进制计数器。-Use NI ELVIS platform to build circuits using Labview programming, design a binary counter.
counter
- 基于我们所熟悉的汇编语言简单计算器的用法代码-simple counter program
counter
- Here is the code for bit counter