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counter
- 实在在开发板上显示的摸60计数器，时钟分频为1s，能在数码管上显示-Development board really feel 60 counter display, the clock frequency of 1s, can be displayed on the digital tube
counter
- 基础的计数器。4位。Verilog HDL-Basic Counter. Four bit.Verilog HDL
counter
- 大计数器的快速实现方法，本例子实现32位计数器，包含测试用例；-Large counter fast implementation, this example a 32-bit counter, including test cases
counter
- 加减计数器实现加减计数功能，可以预置初始值-Down Counter implement subtraction counting function, you can preset the initial value
Counter-strike-DLL
- 反恐精英csol 纯透视源码 dll命令 献给反恐精英修改师门-Counter-strike source DLL
Counter
- best simple counter for verilog modelsim6.5
Visitors-Counter
- visitor counter using the 8051
Counter-winder
- Counter winder. Without turns counter can not do when manually winding the coils of small batches of custom transformers. He uproshaet workflow.
counter
- counter up to 999 using ATMEGA32
Counter
- Verilog program for a counter
counter-with-T_FF
- This is counter with T_FF.
Counting-counter-module-testing
- 采用计数方式计数脉冲，利用系统节拍定时器生成100个脉冲,测试计数器功能-Using counting count pulse is generated using the system tick timer 100 pulses counter function testing
counter
- 本程序为单片机的c语言源程序，可以实现通过单片机的中断实现计数器功能-This procedure for microcontroller c language source code, can be achieved through the realization of microcontroller interrupt function counter
counter
- keil编译，在LM3S9B92开发板上运行的简易计算器-keil+lm3s9b92+ computing counter
xdf-counter
- 只为开放源代码，方便大家 XDF的PHP图形计数器,不适用复杂的数据库，而是采用txt文本数据库，使用更加绿色方便。 另外为大家提供了50中不同风格的选择 counter.txt为访问量,默认为0。 /styles是风格文件目录，里面默认含有50个风格。-Just as open source code, to facilitate PHP graphics XDF counter, is not suitable for complex , instead of u
asynchronous-counter
- 4个触发器构成的异步计数器,采用VHDL语言描述-asynchronous counter
electronic-counter
- 本项目为电子计算器，特点。通过stc1t单片机控制触摸彩屏，实现掌上计算器的功能。彩屏液晶上面显示数字键盘，通过触摸液晶屏实现数字的输入，通单片机计算得出输出结果显示在屏幕上- electronic counter
counter
- 一种裁剪机用的电子计数器，实现了简单的计数器功能。-a electrical counter for the cutter, have a simple count function.
Adding-counter
- 1、 了解二进制计数器的工作原理。 2、 进一步熟悉QUARTUSII软件的使用方法和VHDL输入。 3、 时钟在编程过程中的作用。 - Including synchronous and asynchronous clear enabled adding counter
counter
- 用verilog实现基于FPGA的计数器功能实现-Realization of counter function based on FPGA with Verilog