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用verilog HDL语言或者VHDL语言来编写,实现单周期CPU的设计。能够完成以下十六条指定:
add rd, rs, rt
addu rd, rs, rt
addi rt, rs, imm
addiu rt, rs, imm
sub rd, rs, rt
subu rd, rs, rt
nor rd, rs, rt
xori rt, rs, imm
clo
clz
slt rd, rs, rt
sltu rd, rs, rt
slti
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一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
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一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
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一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
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这个文件中使用verilog hdl简单易懂懂的运用基本运算实现了微型的cpu设计开发过程
-Verilog hdl straightforward to understand the use of basic operations miniature cpu design and development process used in this document
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通过verilog语言设计的简单CPU,可完成加减乘除和算数逻辑移位功能。-By verilog language design simple CPU, to be completed by addition, subtraction, and arithmetic logic shift function.
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10天用verilog实现MIPS_cpu,内有清晰结构图。很好的cpu设计学习资料!-10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!
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RISC cpu设计,verilog语言,PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
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basic cpu design in verilog
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verilog设计的5状态多周期mips
-multiple cycle mips CPU design of Verilog
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