搜索资源列表
jedec_ddr
- Definitions for DDR memories based on JEDEC specs.
ddr_bw_profile
- DDR驱动，一个摄像头产品上的ddr驱动程序-ddr driver
fsl_p2041_rdb
- 风河提供的飞思卡尔P2041 VXworks BSP包，完美支持SATA NAND DDR USB MMC PCI等接口-Freescale P2041 VXworks BSP package Wind River provides the perfect support SATA NAND DDR USB MMC PCI interfaces
PRU_memAccessPRUDataRam
- AM335X PRU例子，介绍如何进行PRU与DDR之间的通信-AM335X PRU example, introduce how to communicate beteween PRU and DDR
atmel-sdramc
- Atmel (Multi-port DDR-)SDRAM Controller driver.
highbank_mc_edac
- DDR Ctrlr Error Registers for Linux v2.13.6.
jedec_ddr_data
- DDR addressing details and AC timing parameters JEDEC specs. -DDR addressing details and AC timing parameters JEDEC specs.
dpm
- switch stack to L1 scratch, prepare for ddr srfr.
realization-of-VGA-display-with-FPGA
- <用FPGA实现VGA显示> 摘要：本文介绍了一种用FPGA结合DDR SDRAM和单片机，在VGA显示器上显示字符、图形信息的方法。-The realization of VGA display with FPGA
qcom-gcc-msm8660
- Header file for the Atmel DDR SDR SDRAM Controller.
AM335x_DDR_register_calc_tool
- AM335X DDR register calc tools
MYmcb_read_write
- 自己编写的一个赛灵思读写DDR的代码，可以正常读写DDR。-I have written a Xilinx DDR write code that can read and write normal DDR.
mem_interface_top_ddr_controller_0
- 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller
st-fsm
- Definitions for the DDR registers.
jedec_ddr
- Definitions for DDR memories based on JEDEC specs.
ddr2.pdf
- JEDEC DDR 2 memory interface specification document
6678
- 集成6678以太网，NANDflash，DDR，定时器，等常规接口的初始化及应用实例。-6678 integrated Ethernet, NANDflash, DDR, timers, and other initialization and application examples conventional interface.
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe
memtester-4.3.0
- 内存压力测试，用于ddr的压力测试，测试芯片的性能问题-memtest for android 4.4 ddr test
XAPP496---Memory
- 基于FPGA的内存设计资料，能给FPGA方便的使用DDR做很好的准备，很好的资源啊！-FPGA-based memory design information, ease of use give FPGA DDR do good preparation, good resource ah!