搜索资源列表
DualPortRam
- VHDL Dpram including clock divider, D4to7, Scan4Digit and of course TOP level as well as testbench info
divide_clk
- 一个简单的分频器的实现，在altera的开发环境下，功能简单，性能可靠-Implementation of a simple divider, in altera development environment, the function is simple, reliable performance
div_freq
- VHDL program of frequency divider of 50hz at 3Hz 50 -> 3Hz for exemple
clkdiv
- -- Clock divider of generic width (default = 4 bits) -- based on counter from Library of Parameterized Modules (LPM) -- Accepts clock signal at clk_in -- Output clk_out has frequency of clk_in/(2^width) -- Specify width in GENERIC MAP when in
16_fenpinqi
- 这是一个用VHDL语言实现的16位分频器，能够实现分频作用，是一个完整的代码，大家可以参详参详。-This is a VHDL language with 16-bit divider, frequency effects can be achieved, is a complete code, we can participate in detailed reference.
2011-03-09
- 基于quartus II cycloneII verilog分频器-Divider based on quartus II cycloneII verilog
freqdiv
- A frequenzzzy divider that divides the clock signal rate with a factor of 25.
Cllk20Mto10
- 分频器，将20Hz的时钟信号分频到10Hz-Divider, the clock signal frequency 20Hz to 10Hz
ADS2008-GFQ
- 本文是电磁场与电磁波专业的同志们的最佳选择，介绍了一个通过ADS2008仿真的功率分配器。-This is the electromagnetic field and wave Professional the best choice for the comrades, describes a simulation of the power divider through the ADS2008.
18-divide-8-divider
- 从ASM状态图可以看出，在state=0时，初始化参数，如果开始信号有效则载入被除数与除数，接着进入state=1状态，首先判断被除数寄存器的高九位是否大于除数，如果是则产生溢出信号，并回到此状态；否则被除数寄存器向左移一位，并进入state=2状态，同样先判断被除数寄存器的高九位是否大于除数,如果是则被数高九位减去除，并被除数最后一位置为1，并回到此状态；否则被除数寄存器向左移一位，并进入state=3状态, 同样先判断被除数寄存器的高六位是否大于除数,如果是则被数高九位减去除，并被除数最后一
divide-time
- Freescale 飞思卡尔 xs128 时钟分频-Freescale Freescale xs128 clock divider
1
- 用硬件实现8×8点阵LED逐点扫描，主要包括时钟电路和分频电路的设计、制作、以及行、列扫描译码电路的设计、制作。-8 × 8 with a hardware implementation point by point scanning LED dot matrix, including the clock divider circuit and circuit design, production, and the row, column scan decoding circuit design
dianzizhong
- 电子信息技术的发展越来越快，电子产品在人们日常生活中的应用越来越普及。时钟是我们日常生活中不可缺少的一部分，本设计主要使用硬件实现电子时钟的计时、校验等功能。本文主要对时钟电路的选择、功能、原理、装配调试和故障分析排除进行阐述。该电子时钟主要从以下六个方面进行设计：脉冲源、整形电路、分频器、计数器、译码器/驱动器和校时电路。-The development of electronic information technology faster and faster, electronic pro
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- 电子数字钟设计实际上是一个对标准频率（1Hz）进行计数的计数电路。振荡器产生的时钟信号经过分频器形成秒脉冲信号，秒脉冲信号输入计数器进行计数，并把累计结果以“时”、“分”、“秒”的数字显示出来。-Electronic digital clock is actually a standard frequency (1Hz) to count the counting circuit. Oscillator clock signal through the divider formed second
di
- 应用VHDL语言编写设计一个正负脉宽可控的4分频的分频器。程序简单易懂；-Application of VHDL language to design a controlled positive and negative pulse frequency divider 4. Procedures are simple and easy to understand
speaker_divider
- FPGA上蜂鸣器的驱动及测试程序,Verilog HDL语言-The divider and test program of the speaker on FPGA, in Verilog HDL language.
ourdev_461286
- 时钟分频器源代码，使用在fpga中，直接可以使用的源代码-Clock divider source code, used in the fpga, direct source code can be used
fenpinqi-VerilogHDL
- 各种分频器的VerilogHDL语言编写，有通过计数器实现的奇分频，偶分频，任意分频-Various divider VerilogHDL language, there is achieved through the odd frequency counter, even frequency, any frequency
Clk_Div
- FPGA分频器的设计，通过修改参数值可以实现各种时钟频率信号。-Divider FPGA design can be achieved by modifying the parameter values of various clock frequency signal.
int_div0
- verilog编写的任意分频器，经过测试好用，准确-divider verilog any written, tested easy to use, accurate