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rida
- 雷达信号分选算法研究及硬件设计实现-本文详细介绍了利用高性能FPGA——-virtex4 和DSP——TMS320C64 16T芯片搭建硬件平台，协同处理实现雷达信号分选的电路，根据电路特点设计了一套完整的分选算法.-he sorting of radar signal
the signal processing technology in the software GPS receiver
- The software receiver is a type of the GPS receiver based on software written on programmable circuits such as DSP or FPGA. Based on the flexibility of software, we can integrate many techniques, update new technologies and modify its parameters when
The-Phase-Locked-Demodulation-
- 利用Altera公司推出的FPGA开发工具DSP Builder，对锁相解调算法中的主要部件：数控振荡器(NCO)、计算反正切的CORDIC模块和FIR低通滤波器进行了单独设计和仿真，最终完成了锁相解调系统的整体设计。-Designed and simulated major components of phase-locking Demodulation Algorithm independently, including: Number Controlled Oscillator(NCO)、
Matlab-Code
- The software receiver is a type of the GPS receiver based on software written on programmable circuits such as DSP or FPGA. Based on the flexibility of software, we can integrate many techniques, update new technologies and modify its parameters when
1756456
- 设计了一种基于TMS320C6455与FPGA 的实时图像跟踪系统，该系统首先采用MAX9526 采集图像，利用FPGA 对图像进行均值滤波，滤波后数据采用乒乓方式传输给DSP。Mean Shift 跟踪算法采用图像像素灰度距离中心点的距离作 为目标特征建立核函数，实现对目标的实时跟踪。实验表明，该系统具有良好的实时性与稳定性。-Designed a real-time image-based tracking system TMS320C6455 and FPGA, the system
XDS100v3-Design-Kit-1.0-Setup
- 压缩包是ti xds100v3 Design kit的安装文件，安装后有原理图、PCB文件，与DSP接口采用FPGA，安装后有源码，是VHDL格式的，支持开源，降低开发成本-Compression package is ti xds100v3 Design kit installation file after installation schematics, PCB files, and DSP interface with FPGA, after installation source is
hpi
- 实现FPGA控制DSP的HPI接口，使用verilog接口-Achieve FPGA DSP HPI interface control, use verilog interface
EMIF
- EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功-EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success
Blink_6713
- DSP6713的LED闪烁程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 LED flashing procedure, including the FPGA interface program, DSP and FPGA to work together.
ExternalInterrupt_test
- DSP6713的中断测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 interrupt testing procedures, including the FPGA interface program, DSP and FPGA to work together.
TIMER_test
- DSP6713的定时器测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 timer test program, including the FPGA interface program, DSP and FPGA to work together.
PLL_test
- DSP6713的PLL测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 PLL test procedures, including the FPGA interface program, DSP and FPGA to work together.
SDRAM_test
- DSP6713的存储器测试程序，包括FPGA的接口程序，DSP与FPGA协同工作。-DSP6713 memory test program, including the FPGA interface program, DSP and FPGA to work together.
FPGA_emif
- 接口模块，通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块，每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器，寄存器功能可自定义。模块还包含两个全局寄存器，可实现全局复位，中断等功能。该模块以应用于实际的项目中，目前运行良好-FPGA to emif
data_inout_port
- FPGA的I/O接口方向控制的设计，主要应用于与DSP/CPU等接口。-FPGA s I/O interface design direction control, mainly used in the DSP/CPU and other interfaces.
dsp_link_tx16
- FPGA到TS201的link_port接口，以16位的数据格式传输到DSP。-FPGA to TS201 s link_port interface, 16-bit data format for transmission to the DSP.
51--AVR--MSP430--PIC--STM8--STM32
- 各种单片机(51、AVR、MSP430、PIC、STM8、STM32)、ARM、DSP、TFT彩屏、C语言，WiFi小车，FPGA、LINUX、机器人,CAD、VB、Protel99、Protues、Unix、UCOSII等各种视频教程超800G-Various microcontroller (51, AVR, MSP430, PIC, STM8, STM32), ARM, DSP, TFT color screen, C language, WiFi car, FPGA, LINUX, ro
HAPF_SLAVE2
- 高压链式SVG控制用FPGA的verilog程序,其中包括SPI，16路SCI同步通讯模块程序，保护自锁功能程序，基于滞环的无功功率检测和补偿策略；还包括FPGA和DSP之间通过总线方式进行数据的快速交互等；程序完整-SVG high voltage chain of verilog FPGA control procedures, including SPI, 16 road SCI synchronous communication module procedures to protect
PAPER2
- FPGA+DSP异构视频处理系统中基于SRIO的数据高效传输方法-FPGA+ SRIO data transmission method efficient heterogeneous DSP based video processing system
FIFO_POLL
- DSP通过EMIF接口访问FPGA内部寄存器（FD6713开发板）-DSP access the internal registers in FPGA via EMIF interface (FD6713 Development Board)