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ChapterXonthetestmachine(be)
- 第十章 上机实验(定)实验一 系统响应及系统稳定性。 实验二 时域采样与频域采样。 实验三 用FFT对信号作频谱分析。 实验四 IIR数字滤波器设计及软件实现。 实验五 FIR数字滤波器设计与软件实现 实验六 应用实验——数字信号处理在双音多频拨号系统中的应用 -Chapter X on the test machine (be)
FIR_TEST
- 应用matlab 软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块,并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真。-About such key algorithms as CIC, HB, FIR of each module in down- conversion, discussion, abstraction and summarization are given in this paper. Using the MATLAB software, we des
Lab0501-FIR
- 窗函数设计FIR数字滤波器的原理 线性相位FIR数字滤波器算法-FIR
FIR
- 已知一低通滤波器的采样率为2KHz,通带为500Hz,阻带为600 Hz,带内波动3dB,带外衰减-50dB,滤波器的相位具有线性特性,具体幅频特性见下图。要求用等波纹方法设计出该FIR滤波器,然后用TMS320C54x汇编语言编程,并在CCS下调试实现该FIR滤波器。-A low-pass filter known to the sampling rate of 2KHz, passband to 500Hz, stopband to 600 Hz, with fluctuations wit
cic
- 当前工程上广泛采用了一种高效滤波器,即CIC(cascaded integrator-comb filter)将其作为第一级来实现抽取、低通滤波。第二级再用一个普通的FIR滤波器就实现使后端设备工作在较低的频率下且硬件花销少、功耗也很低。-Widely used in the current project, a highly efficient filter, that is, CIC (cascaded integrator-comb filter) as the first level t
FIR
- this a souce code for computing FFT on C6xx series ti dsp kits-this is a souce code for computing FFT on C6xx series ti dsp kits
T-CAS
- Efficient FIR Filter Architectures Suitable for FPGA Implementation Joseph B. Evans Telecommunications & Information Sciences Laboratory
RLSIdentifyFIRFilter
- source code for identifying the FIR filter using the RLS algorithm-source code for identifying the FIR filter using the RLS algorithm
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- 基于FPGA实现FIR数字滤波器的研究 -FPGA-based realization of FIR digital filter FPGA-based realization of FIR digital filter
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- 基于FPGA分布式算法的FIR滤波器的设计 基于FPGA分布式算法的FIR滤波器的设计-FPGA-based distributed algorithm of the FIR filter design distributed algorithm based on FPGA Design of FIR Filters
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- 基于FPGA的高速高阶FIR滤波器设计 基于FPGA的高速高阶FIR滤波器设计-High-speed FPGA-based FIR filter design for high-end high-end high-speed FPGA-based FIR filter design
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- 基于FPGA的FIR数字滤波器的设计与实现,基于FPGA的FIR数字滤波器的设计与实现-FPGA-based FIR digital filter design and implementation of FPGA-Based FIR Digital Filter Design and Implementation
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- FIR的FPGA实现及其Quartus Ⅱ与MATLAB仿真 FIR的FPGA实现及其Quartus Ⅱ与MATLAB仿真-The FPGA realization of FIR and its Quartus Ⅱ and MATLAB simulation FIR realization of the FPGA and Quartus Ⅱ and MATLAB simulation
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- FIR数字滤波器的FPGA实现2 FIR数字滤波器的FPGA实现2-FIR digital filter FPGA to achieve the 2 FIR digital filter of the FPGA to achieve 2
65jie
- 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点,但是要占用大量的资源。在多阶数的亚高频系统设计中,使用并行结构并不合算,但亚高频系统需要较高的处理速度,而串行架构往往达不到要求,因此,结合串并这两种设计方法的长处,在使用较少的硬件资源的同时实现了较高的处理速度,这里说明一种65阶八路并行、支路串行FIR滤波器的设计(实际使用了1个乘法器,8个乘累加器,一个累加器)。-String and FIR filter design: parallel FIR filter with a
DSPSRC
- Audiocfg_FIR--利用dsp6713实现fir滤波 Audiocfg_IIR--利用dsp6713实现iir滤波 fileout--烧写flash必要的准备 SDRAM--6713读写SDRAM simfft--6713实现fft变换 sstpro--烧写flash Timer_GPIO--通过定时器实现led灯周期闪动 Videocfg--视频配置-Audiocfg_FIR- the use of fir filter dsp6713 ach
FIR_FILTER_C
- 使用C语言实现FIR滤波器,包括基本滤波器,使用循环缓冲区的滤波器等-The use of C language realization of FIR filters, basic filters, use of filters, such as buffer zone
fir
- 利用Verilog语言编写的FPGA作为数字fir滤波器的程序,在编译器中调试通过,可以作为模块调用。-the model of fir digital cr which is written of verilog language.
Windowed_FIR_Filter_Design
- This examples shows the Transfer Function of a FIR windowed filter given the Filter Type. The parameters are different for each type and may be changed to investigate their effect on the response. [This example requires the Full or Professional ve
halfband_1
- remez算法设计半带FIR滤波器,对半带滤波器,通带和阻带权值惩罚函数要相等-remez algorithm design half-band FIR filter