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Tutorial_5
- 一个序列检测器的FPGA设计实验，通过LED灯显示，基于Spartan-3e开发板-The sequence detector will look for the input series “10010.” LED’s will show how much of the series has been detected and when the entire series has been entered an additional LED will come on. Circuit input
clk_div3
- 在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。-Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.
EDAdianzizhong
- 基于FPGA的数字电子钟设计，有VHDL语言实现其功能-FPGA-based design of digital electronic clock with VHDL language function
en_ctrl(u)
- 此源码为基于FPGA的液晶屏显示的数字钟程序，程序包含强大的液晶显示控制模块。-The source code for the FPGA-based LCD screen display digital clock program, the program includes a powerful liquid crystal display control module.
clock_VHDL
- 主要供学习FPGA的人员学习如何写VHDL程序之用，该程序实现了时钟的二分频等功能。-Primarily for learning FPGA-VHDL program to learn how to write use, the program achieved the second clock frequency and so on.
clock_vhdl
- 使用quartus ii开发的FPGA电子时钟的VHDL源代码，分模块写法，在1602液晶上显示，具有走时，调节时间功能-Using quartus ii the development of electronic clock FPGA VHDL source code, sub-module written in the 1602 LCD display, with travel time, settling time function
ADC0809
- 基于VHDL语言，实现对ADC0809简单控制。ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟-Based on VHDL language, to achieve simple control of ADC0809. ADC0809 no internal clock, an external 10KHz ~ 1290Hz clock signal, where
AX_Clock_Dithering_AN
- Frequency fine tuning and clock dithering using ACTEL FPGA devices.
FPGAclock
- FPGA设计中，时钟设计是很重要的一环，本文主要描述了FPGA设计中时钟设计的重要事项-FPGA design, clock design is a very important part, this paper describes the design of FPGA design, the clock on important issues
VHDLclokedisplaycounter
- 基于秒表改换的测频率计，分为三个项目立化，分别为计算、时钟、显示。用于FPGA试验台-Change based on the measured frequency meter stopwatch, set of three projects, namely, computing, clock, display.
dfilter
- 用FPGA实现信道化接收机算法，共256个信道，处理时钟40M，时分复用完成算法实现-FPGA implementation using channelized receiver algorithm, a total of 256 channels, processing clock 40M, time division multiplexing algorithm to complete
yt7132_clock
- 用VHDL语言编写的12/24小时时钟，利用EDA系统软件QuartusII环境下基于FPGA/CPLD的数字系统设计方法-VHDL language with the 12/24 hour clock, the use of EDA software QuartusII environment based on FPGA/CPLD design of digital system
VGA2
- VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
DIGITAL_CLOCK_TEST
- 数字钟的FPGA实验，挺好用的，修改了一般代码的频闪问题，时间不准的问题，应用于CYLONE2平台及外借数码管-Digital clock FPGA experiments, very good use, modify the general code of strobe, time allowed to question, and the loan application CYLONE2 digital platform
FPGAlarge-scaledesign
- 利用 FPGA 实现大型设计时，可能需要FPGA 具有以多个时钟运行的多重数据通路，这种 多时钟FPGA 设计必须特别小心，需要注意最大时钟速率、抖动、最大时钟数、异步时钟 设计和时钟/数据关系。设计过程中最重要的一步是确定要用多少个不同的时钟，以及如何 进行布线，本文将对这些设计策略深入阐述。-Using FPGA to achieve large-scale design, may need to run the FPGA with multiple clocks to mult
Final
- This module contains a digital clock which can enables clock setup option and up to four alarms. This was targeted Virtex-5 FPGA (ML501) and interfaced with LCD display. and center, north and east push buttons.
double_dcm
- 这个主要是在xilinx FPGA中双DCM连接的问题，这个问题网上资料很少，自己研究后并且仿真之后可以实现两个dcm的正常工作，实现倍频和时钟的反相-This is mainly the double in xilinx FPGA DCM connection problem which little information online, their own studies and simulation can be achieved after the normal work of the
LCD1602shizhong
- 基于FPGA设计的1602显示的时钟，分为几个模块，VHDL语言-FPGA-based design 1602 show the clock, is divided into several modules, VHDL language
topclock
- 基于FPGA的数字钟设计，带有正点报时任意时刻闹钟-Design of FPGA-based digital clock, alarm clock with a punctual timekeeping at any time
driverfromlcd
- 一个用FPGA控制12864液晶输出时钟信息代码，可以根据自己的需要更改。-A control with the FPGA code 12864 LCD output clock information can be changed according to their needs.