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I2C_slave_model
- 完整的I2C slave model以及spec詳附在內,適合想利用verilog開發此類傳輸的人參考 -integrity of the I2C slave model and spec are attached, want to use Verilog for the development of such transmission of reference
I2CSlave
- Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
I2Cslave
- i2c slave,这个是I2CBUS接收端的源代码，由VERILOG写成，经过综合和调试
i2c_p_altera
- altera i2c slave ip核verilog 编写
i2cslave
- 此代码是I2C Slave的Verilog源代码,已经经过上板调试，没问题。-This code is the I2C Slave of Verilog source code, has been on the board debugging, no problem.
I2C_master_code
- 主要介绍，I2C总线主设备发送数据给从设备，代码实现是用Verilog语言实现的，对硬件设计者有很大好处-Introduces, I2C bus master to send data to the slave device, code is implemented in Verilog language, the hardware designer of great benefit
i2cslave_latest.tar
- I2C从机控制器Verilog源码，实现标准I2C从机接口-I2C slave controller Verilog source code to achieve the standard I2C slave interface
i2cSlave_2
- Verilog source for i2C Slave device
i2c_fsm.v
- This a verilog module which describes a i2c slave fsm with one-hot encode.-This is a verilog module which describes a i2c slave fsm with one-hot encode.
i2c_slav_tb4
- verilog, i2c slave, 两个输入端口，可自由切换。-verilog, i2c slave, two input ports are free to switch.
i2c_reg
- 用verilog实现的一个从机的I2C通信模块，测试通过可用，已经在项目用的了！-Using verilog achieve a slave I2C communication module, the test is available, has been used in the project!
i2c_slave
- 使用verilog语言实现I2C Slave功能模块，带有地址匹配和8位寄存器和8位数据读写。-verilog HDL I2C Slave function module with address matching and eight 8-bit data registers and write.
i2c_slave
- I2c slave 16 bit data verilog 代码-i2c slave verilog code
i2c_slave
- Verilog实现的i2c从设备仿真模型，只需修改控制码就可直接使用，自用-Verilog implementations i2c slave device simulation models, simply modify the control code can be used directly, for personal use
OV7725_i2c_timing_ctrl
- iic接口verilog HDL代码，经过测试验证，在OV7725控制接口上验证- //i2c interface output i2c_sclk, //i2c clock inout i2c_sdat, //i2c data for bidirection //user interface input [7:0] i2c_config_size, //i2c config data counte output reg [7:0] i2c
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
i2c_slave_model
- I2C从控制器verilog代码，主要用于混合信号ASIC的寄存器配置接口(I2C slave module in verilog)
i2c_wishbone.tar
- verilog i2c master wishbone slave wrapper
i2c_slave
- I2C从机模块，支持多种I2C模式，稳定成熟，方便使用。(I2C slave module supports multiple I2C modes, which is stable, mature and convenient to use.)