搜索资源列表
cw
- 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的-signal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for alte
PS2_IP_CORE
- 该IP核是一个ps2键盘的源代码（vhdl语言）-The IP core is a ps2 keyboard source code (vhdl language)
pci_express_decrypt
- Decrypted PCIexperss ip core x1 x4 x8
RealizationofdigitaldownconversionbyFPGA
- 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the prepa
FFTVHDl
- 基于FPGA的fft实现 摘要：本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核，代替传统DSP芯片或高性能单片机，实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core
DE2_pio
- altera University Program 的 Avalon总线的IP核，GPIO，可以直接解压以后挂载在Avalon总线上-altera University Program of the Avalon bus IP core, GPIO, after decompression can be directly mounted in the Avalon bus
vhdl-MIPS
- Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
EXAMPLs
- 康芯公司FPGA开发板的 一些资料 有cpu8051IP核-Kang FPGA development board core company information cpu8051IP some nuclear
C8051_IP
- 一个简单IP核，含4Krom，经测试可方便使用-A simple IP core, with 4Krom, can be easily tested using
Guagle_wave
- altera 的存储器IP核的初始化mif文件生成器，可任意点数和任意波形-Initial altera s ip core of ROM or RAM need .mif file,use this software you can generate it ,any wave
IntegrationofSystem-On-ChipSimulationModels
- SOC仿真模型的整合 丹麦技术大学 硕士论文 通过SystemC来建立SOC仿真模型-Integration of System-On-Chip Simulation Models Technical University of Denmark Master Thesis Reaching deep sub-micron technology within the near future makes it possible to implement comple
cpu86model
- This is intel 8088 x86 IP core, contain software complier & modelsim testbench
altera_up_avalon_ps2
- Altera公布的大学计划中基于VHDL的ps2的IP核！-Altera University Program announced VHDL-based IP core of the ps2!
altera_up_flash_memory
- Altera公司大学计划中公布的基于VHDL的通用flash的IP核！-Altera' s University Program announced in the flash-based VHDL generic IP core!
PCi_Bridge
- Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
shiboqi(chugao)
- 这个方案是在FPGA中嵌入51单片机IP核，通过51单片机的控制来很方便的实现对数字存储示波器的显示和控制！是我国赛训练的一个题目！-This program is embedded in the FPGA microcontroller IP core 51 through 51 SCM control to easily realize the digital storage oscilloscope display and control! The training of our race
FPGA51he
- 这是一个51单片机嵌入在FPGA中的ip核，这个核它完全兼容我们普通的8051单片机，也就是说程序在这个上面一样可以跑起来-This is a 51 microcontroller embedded in the FPGA in the ip core, the core is fully compatible with our ordinary 8051, that the program can run up the same as above
AlteraSdramIP
- Altera Sdram IP 源码.rar-Altera Sdram IP source code. Rar