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dual_ram
- 在ISE中测试双端口RAM的源码,结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
USB-IPcore-Verilog
- USB IP 核设计,Verilog,ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
E4_4_IIR4Functions
- 用verilog语言实现的一个IIR滤波器,因为现在的ise等工具中没有包含相关的ip核,所以需要手动设计。 -With verilog language to achieve an IIR filter, because now ise and other tools do not contain the relevant ip kernel, so the need for manual design.
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
xilinx_lib.tar
- 用于modelsim仿真的xilinxfpga平台IP库,以ise 13.x为基础制作,在modelsim10下验证通过。(xilinx IP core library for modelsim simulate, based on ise 13.x, verified in modelsim10.)
parallel_norflash_test
- ISE工程,并行nor flash的读、写、擦出,其中有个调用FIFO16-16的IP核,已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
dds
- dds算法,调用xilinx IP ,ise(DDS algorithm, call Xilinx IP, ISE)
ffft128点
- fft128点Verilog工程,非ip核ISE工程