搜索资源列表
mult3
- this the multiplier 3 module for the reed solomon encoder-this is the multiplier 3 module for the reed solomon encoder
mult4
- this the multiplier 4 module for the reed solomon encoder-this is the multiplier 4 module for the reed solomon encoder
ex
- 用HDPLD实现的高速并行乘法器，其输入为两个带符号位的4位二进制数- HDPLD implementation with high-speed parallel multiplier, the input symbols with two 4-bit binary number
Boothmultiplier
- 布斯乘法器的语言描述功能违反外 暗暗达到-Booth multiplier described in the language
Mars_EP1C6F_fundemantal_demo
- FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。-FPGA development board source. Chips for the Mars EP1C6F.VHDL language. Can achieve some of the basic functions. Such as multiplier, adder, such as MUX.
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Protel
- 内含常用原理图的封装及PCB的封装.对于您能起到事半功倍的效果-Includes schematic diagram commonly used packaging and PCB assembly. You can play for a multiplier effect!!!
THREEBITMUL
- 实现多字节的十六制数的相乘，入口为被乘数高字节地址，乘数高字节地址，字节数，出口为积最高字节地址-The realization of multi-byte number of the system multiplied by 16, the entrance of the high-byte address for the multiplicand, the multiplier high byte address, byte count, exports the highest byte a
Multiplexer
- 这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.
multi8x8
- VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
EPM1270_multiplier
- VHDL 乘法器 源代码，很好的VHDL 入门学习例程序-Multiplier VHDL source code, a good learning example VHDL entry procedures
MultiplicadorSHIF
- This code creates a 8 bit full multiplier.
adder
- 采用加法树流水线乘法构造八位乘法器，并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
cfq8
- VHDL语言编写8位乘法器非常实用语言绝对正确经过仿真的-VHDL language is very practical 8-bit multiplier is absolutely correct language after simulation
3-bit_multiplier
- 用ASM原理做二進位3-BIT乘法的乘法器，內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 3-BIT multiplier, the input file containing a sample.
8-bit_multiplier
- 用ASM原理做二進位8-BIT乘法的乘法器，內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 8-BIT multiplier, the input file containing a sample.
MultBCD
- Multiplier BCD - vhdl-Multiplier BCD- vhdl
Moltiplicatore-complementi
- complement of multiplier
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and