搜索资源列表
xd_lcd_comp
- 一款240＊128的LCD模块在ALTERA FPGA NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考
Usb_ISP1362
- 飞利浦公司Usb芯片ISP1362在nios中的IP核，可以用-Philips Usb-chip ISP1362 in nios in the IP core, you can use
DoubleNIOS2IP
- 基于双NIOS II 的IP 无线收发机，双NIOS通信，无线收发机-The IP-based two-NIOS II wireless transceiver, dual NIOS communications, wireless transceivers
pwm
- 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
LCD12864IP
- 12864的IP，在艾米电子工作室的nios开发板上可执行-12864 of the IP, in the electronic studio nios Amy executable development board
AIC23IP
- AIC23的IP核，提供ＮＩＯＳ ＣＰＵ与FPGA 的通信方式-AIC23' s IP core, providing NIOS CPU means of communication with the FPGA
quartus_IPcore
- 这15个Quartus的ip核里面有AVR，I2C，sdram，arm，usb，PCI等ipcoure，相信用过ipcore的人都知道这个的重要性，尤其是在NIOS嵌入硬件以提高速度的时候，这些事非常有用的。毕竟这些事人家封装起来的，肯定比自己去编好吧，献给用Quartus的好盆友，希望对你们有用。-free ipcoure
StandardSystem_design
- 基于Avalon总线接口的PWM IP Core 设计 nios ide 环境下可调占空比和周期。-PWM IP Core
tcpudp
- NIOS IDE环境下 网络芯片ENC28J60驱动程序与TCP/IP协议栈，实现与上位机的TCP，UDP通信。-NIOS IDE environment, the network chip ENC28J60 driver and the TCP/IP protocol stack to achieve communication with the host computer s TCP, UDP.
pwm
- PWM的NIOS II IP核设计源文件，其频率和脉宽均可控-PWM IP core design source files of the NIOS II , It s frequency and pulse-width words can be controlled
DE2_NIOS_HOST_MOUSE_VGA
- 基于nios的vga显示实验，自制的ip核。可以按照自己的需求改写ip-Nios to vga display ip nuclear experiments, homemade. Can be rewritten in accordance with their own needs ip
yinpine2
- 基于NIOS2的VGA接口IP核，具有很好的借鉴性和参考性-NIOS VGA IP
tcpip
- nios中的tcp/ip网络编程。值得细看，绝对能运行成功-nios in tcp/ip network programming. Worth a closer look, absolutely can run successfully
LCDIp
- 一款TFT-LCD驱动的IP核，可以嵌入到NIos系统中，可以使用的。-A TFT-LCD driver of the IP core
DE2_115_WEB_SERVER_MII_ENET0
- Simple HTTP server using sockets interface of NicheStack TCP/IP and NIOS II SCPU to serve HTML, JPEG, GIF PNG, JS, CSS, SWF, content using RGMII on DE2-115 board
yinpinxinhaofenxiyi1233412
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核的基于FFT的音频信号分析仪-Based on Altera Cyclone II series FPGA embedded high-performance embedded IP core (Nios) soft core processor FFT-based audio signal analyzer
HY57V64_control
- 本代码用verilog而不是直接在nios中用ip核来实现HY57V641620FTP-6的读写，时序完全正确，从串口输出来验证的数据完全正确。附带说明和参考资料。希望对您有帮助。-This code is used instead of directly in verilog ip core nios used to achieve HY57V641620FTP-6 reading and writing, the timing exactly right, from the serial d
IrDA
- DE2开发板所付实例，红外无线通信IP核，嵌入式IP核。-altera nios II
Md5Sopc
- 在Altera平台上实现Md5算法的IP核 modelsim进行MD5硬件代码的仿真和测试 quartusII 和nios软件实现ip核和驱动程序 已经测试程序的仿真和测试 代码调试通过 -Md5 algorithm simulation and test implementation in the Altera IP core platform modelsim the MD5 code simulation and test hardware and quartusII ip nios so