搜索资源列表
leap1
- 基于quartusII软件的闰年判断器的实现,运用vhdl语言描述-Software leap judgment based quartusII the realization, using vhdl language descr iption
vote5
- 基于quartusII 软件设计的五人表决电路实例,运用vhdl语言描述-Software design based quartusII five voting circuit examples, using vhdl language descr iption
fdiv
- 基于quartusII实现1 HZ分频,vhdl语言描述,可实现对1hz的34556分频-Based quartusII achieve 1 HZ divider, vhdl language descr iption can be realized on the 34556 1hz divide
LED_test
- QuartusII下面的一个简易LED控制程序,新手可以参考一下-QuartusII following a simple LED control program, and newcomers can reference
EDA 四路模拟信号循环采集
- 对思路模拟信号进行循环采集并在Signal Tap 上显示出来。利用QuartusII软件编程,分为几个模块,都有详细的代码和仿真图。已经试验验证正确。
jiaotongxinhao
- vhdl语言编写的,在QuartusII下,交通信号灯控制器-vhdl language, in QuartusII, the traffic signal controller
ledarray
- 用vhdl语言,在QuartusII下,点阵显示欢迎使用系统-Using vhdl in QuartusII, the dot matrix display welcome to use the system
巴克码VHDL
- 非常详尽的VHDL语言编写的巴克码发生器,已在QuartusII上运行,检查无误
mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
keyqudou
- fpga verilog hdl 设计键盘去抖动程序,设计环境quartusii 9.0。仿真绝对通过。-fpga verilog hdl design keyboard to jitter program design environment quartusii 9.0. Simulation absolutely pass.
mux4booth
- fpga 使用verilog hdl 语言,quartusii 9.0编程环境,使用2booth算法设计的4bit乘法器。可以扩展为16bit乘法器。-fpga verilog hdl ,quartusii 9.0 ,2booth 4bit
top_module
- fpga 使用verilog hdl 语言,quartusii 9.0编程环境,设计的4个led灯分别实现不同功能,然后由一个顶层文件调用,完成总的设计。-fpga using verilog hdl language, quartusii 9.0 programming environment designed four different functions, respectively, led lights, followed by a top-level document called,
Qsys_altera
- altera的quartusII中,最好的qsys入门学习资料-altera' s quartusII, the best qsys learning materials
Quartus-VHDL-lms
- 使用VHDL语言在quartusII中实现自适应滤波算法-The filtering algorithm
bit7_Binary_to_BCD_LED
- 二进制转十进制BCD码 Verilog语言 quartus-Binary to decimal BCD code Verilog language quartusII
zdsylj
- 自动售饮料机,在quartusII平台上实现verilog源代码。很好用。-Beverage vending machine, quartusII platform to achieve verilog source code. Good use.
sdram
- sdram的quartusii实验源代码,和大家分享。很好用,我在自己的开发板上实现了他的功能,大家试一下。-sdram of quartusii experiment source code, and share. Very good, in my own development board realize his function, we try.
dgnszsz
- 多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。-Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.
hlh
- 绿灯、黄灯和红灯,交通灯实验veril源代码,与大家分享,在quartusII平台上实现。-Green, yellow and red lights, traffic lights experiment veril source code, to share with you, in quartusII platform.
zwcfq
- 带置位和复位端的1 位数据锁存器,源代码verilo实现,在quartusII平台上,大家试试看。-With set and reset terminal a data latch, the source code verilo achieve, in the quartusII platform, we try.