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ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
Dual-Role.A-Device.State.Machine
- OTG HNP State Machine Pseudo Code-Dual-Role A-Device State Machine
DVDT_MORE
- 基于FPGA有限状态机的数据采集系统，实现对高速AD转换的控制。-FPGA-based finite state machine of the data acquisition system for high-speed AD conversion control.
mmi
- 手机mmi状态机，包括打电话、发短信、SAT-State machine of mmi of mobilephone, it s including Call, SMS, SAT etc.
telephone
- 实现长途电话，市话的计时，还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve
ProducerConsumerExample
- 类似一个可乐销售机系统，LabVIEW网络讲坛《状态机》(State Machine)下集里面用作例子-Producer Consumer Example This particular example, a simulated soda machine, uses an event structure in the producer loop to register user input (depositingclicking on quarter, dime or nickel), an
example9
- 用 epm240 驱动 adc0804 这个芯片,本实验用状态机来控制。-Epm240 Driver adc0804 with this chip, the state machine to control the experiment.
QHSM
- 笔记有关quantum hierarchical state machine的学习内容 共分成三个部分 1.hierarchical state machine 2.Quantum FrameWork 3.Implement 参考书目 Practical Statecharts in C/C++ Quantum Programmming for Embedded Systems Miro Samek, Ph.D.-Notes on quantum hiera
ACsearch_DPPcompact_with_driver
- AC多模式匹配算法的CUDA实现 Aho-Corasick算法是基于有穷状态自动机的多模式匹配算法-AC multi-pattern matching algorithm CUDA implementation Aho-Corasick algorithm is a finite state machine based on the multi-pattern matching algorithm
FSM
- finite state machine design
lsm
- Liquid State Machine toolbox
statemachine
- 一个用vhdl语言写的交通灯控制的例子，可以很好的学习vhdl语言中状态机的使用。-Written in a language with vhdl traffic light control case study can be a good vhdl state machine language to use.
Three-stage-state-machine
- 状态机是逻辑设计的重要内容，状态机的设计水平直接反应工程师的逻辑功底，所以许 多公司的硬件和逻辑工程师面试中，状态机设计几乎是必选题目。本章在引入状态机设计思想的基础上，重点讨论如何写好状态机。-State machine is an important part of logic design, state machine design engineers a direct response to the logic level of skills, so the company s ha
Determine-Warning-State-Machine
- 气象站 温度 风力 数据处理分析 判断警告 状态机-Weather warnings state machine to determine the temperature of wind
State-machine
- 状态机，北航c2的某一次作业题，经测试，能通过所有测试点-State machine, an operation of a Northern question c2, tested, pass all the test points
State-machine-keys
- 状态机按键，带PROTEUS仿真。对初学者很好-State machine keys
state-machine-code
- 用Altera Quartus II 的VHDL语言完成的状态机控制步进电机的程序员代码-The use of Altera Quartus II VHDL language to complete the state machine code programmer stepper motor control
state-machine-
- VHDL语言状态机的源程序，有助于学习VHDL语言的状态机-VHDL state machine of the source language to help learn the language of the state machine VHDL
Verilog-state-machine
- 状态机采用 VerilogHDL 语言编码，建议分为三个 always 段，本文档就是详述其原因-VerilogHDL language code using the state machine, the proposed section is divided into three always
Sequence-Detector-State-Machine
- 状态机序列检测器设计，包含程序在内，该程序是检测1101-Sequence detection state machine design, including the program included, the program is to test 1101