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seg7
- 通过Verilog语言,显示七段数码管,在cycloneI上能正确显示-Verilog language, showing seven-segment LED display correctly, cycloneI
test12
- 自己用VerilogHDL语言编写的时钟程序,包括时钟进位计数模块,数码管显示模块和闹钟模块。在cpld芯片上经测试有效(开发环境没找到VerilogHDL,就选了VHDL,其实他们不一样的……)-Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been te
ds_test12
- 在Verilog语言下用FPGA驱动DS18B20,带数码管显示,带LED报警,有报警值调整功能。这个是本人调过的,原版调通代码没改的,绝对能跑通。建议用QuatusII全编译后看一下RTL图就能理解程序是怎么工作的。-A Demo of DS18B20 on FPGA.
welecome_key
- Verilog编写的按键控制串口的发送数据,接收的数据通过数码管显示-Verilog prepared by the buttons control the serial port to send data, receive data through the digital display
SEG7lED
- 基于verilog的7段数码管显示控制,实现数字显示。-7 seg led displaying control based on verilog
Calculator.v
- Verilog实现简易计算器,用数码管显示结果-Verilog achieve simple calculator, with digital display results
LED_Display
- 基于FPGA的八段数码管显示的verilog程序,采用的是altera公司的EP2C8Q208芯片。-FPGA-based verilog eight digital tube display program, using altera company EP2C8Q208 chips.
EX4
- 基于可编程器件设计的一个电路,可以实现矩阵键盘的连续输入和数码管的移位显示功能。 1)连续按下按键0~9 、A~E,数字和字母将依次显示在4 位数码管上。 2) 按下F 时,数码管上不显示 F,当前显示的数字按一定频率闪烁。直至按下其他数字和字母后,再次稳定显示4 个数字。以此类推。 3)任何时刻按下实验板上的RST 键,可将电路清零. -Verilog, QuartusII run correctly, can be downloaded to the FPGA. Could
juzhenjianpan
- verilog写的一个5乘5键盘扫描程序,并可以利用数码管实现对于的0到24的显示-verilog to write a 5 x 5 keyboard scanning procedures, and can be implemented for the use of digital tube display of 0-24
clock
- verilog hdl 编写的八位数码管24进制的数字钟,含清零功能-verilog hdl written eight digital tube 24 hex digital clock, with clear function ...
seg7
- fpga上nios处理器avalon总线数码管驱动,包含任务逻辑,寄存器,和接口的verilog HDL描述-fpga nios processor avalon bus on digital tube driver, including the task logic, registers, and interfaces verilog HDL descr iption
nexis1
- 用Verilog HDL 状态机实现的驱动数码管显示,是个很不错的模块,可以直接用-Using Verilog HDL state machine driven digital display, is a very good module, can be directly used
display
- 实现了Verilog语言驱动数码管,扫描稳定。无抖动。可是很清晰的显示字符-Implements the Verilog language-driven digital control
shumaguan
- 基于FPGA,使用verilog语言模块设计实现数码管计数-Based on FPGA, using verilog language module design and implementation of digital tube count
shumaguan
- verilog 写的,基于CPLD 的数码管实验,输入端是430单片机,cpld做了38译码器和8位所存-verilog written CPLD-based digital tube experiments, the input is 430 single, cpld made 38 decoder and 8 kept
smg_8
- 基于verilog HDL预言的8段数码管驱动程序,模块化-Predictions based on verilog HDL 8 digital tube driver, modular
PWM
- 程序PWM_rate1可以输出占空比可调的方波,并把占空比用数码管显示出来。-verilog pwm
shumaguan
- FPGA中数码管的使用,verilog程序,已经显示成功-The use of the FPGA digital tube, verilog program, has been shown to successfully
seg7_8
- fpga cpld verilog hdl 语言 代码程序 数码管 控制
clock_project
- verilog 时钟 1602和数码管 显示-verilog 1602 and digital display clock