搜索资源列表
quartus_works_first
- 基于verilog语言的，FPGA程序，实现可暂停的计时器与数码管显示功能，计时范围0~99秒，精度0.01秒，在EP1C3T100C8上亲测通过-Based verilog language, FPGA program implementation can pause the timer with digital display function, time range from 0 to 99 seconds, precision 0.01 seconds, measured by the
quartus_works_second
- 基于verilog语言的，FPGA程序，实现频率计与数码管显示功能，转换频率48M，精度1Hz，量程1Hz~9999Hz，有欠频率和超频率提示，精度与量程可随外部设备改变而改变，在EP1C3T100C8上亲测通过-Based verilog language, FPGA procedures to achieve frequency meter with digital display, switching frequency 48M, precision 1Hz, range 1Hz ~ 99
miaobiao
- 一个精确的秒表，显示在数码管上。对于初学者使用verilog有很大的帮助，同时注释很详细。-An accurate stopwatch displayed on the digital pipe. For beginners verilog a great help, and very detailed notes.
adc0809
- ADC0809转换器的verilog版本,运用在ISE上，直接可用（注意没有考虑频道问题），结果显示在数码管里（十进制）-Verilog version ADC0809 converters, used in the ISE, directly available (note does not consider channel problems), the results are displayed in the digital tube (decimal)
Vhdl1
- VHDL语言编写Verilog，实现数码管上数字循环显示-VHDL language Verilog, to realize the digital tube display digital loop
Key-and-digital-tube-display
- 按键和数码管显示，FPGA的verilog代码-Key and digital tube display
Multiplier-digital-tube-display
- 乘法器数码管显示，FPGA的verilog代码-Multiplier digital tube display
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display
number_mod
- 以verilog设计最大为99数字在2个数码管资源上的显示，采取的方法是同步动态扫描。-Verilog design to a maximum of 99 digits displayed on two digital resources, the approach is synchronous dynamic scanning.
test_led
- Verilog语言的24小时计数器，数码管显示，按键调时，在CPLD上调试正常。-Verilog language 24-hour counter, digital display, when the key tone on CPLD normal debugging.
led_flow
- 跑马灯的VERILOG程序编程，实现了数码管的一次点亮-VERILOG programming Marquee achieve a digital one is lit
jiajian
- 利用Verilog语言编写的按键实现数码管显示数字的加减，通过三个按键分别实现加1和减1操作 以及复位操作，BASYS2开发板验证。-Verilog language use buttons to achieve digital display digital subtraction achieve plus one and minus one operation and reset operation, BASYS2 development board were verified by thr
clock
- 用verilog编写的电子钟，里面用各个模块实现，使七段数码管上显示小时和分钟，读秒用数码管的点表示-Using verilog electronic clock, with each module inside, so the seven-segment digital display hours and minutes on the tube, with the point of a digital countdown said tube
key_ctr_smg
- 使用altera公司的处理器，使用verilog语言编程，程序功能是按键控制数码管-Use altera' s processors, using verilog language programming, the program features a digital key control
smg
- 数码管设计：顶层为数码管的封装，用户可自己分配引脚。很实用的Verilog程序。-Digital design: the top of the digital package, the user can assign pin himself. Very practical Verilog program.
number_16
- 该功能是：用四位二进制数作为输入，在FPGA上的七段数码管上将0到F这十六个数输出，用verilog语言来实现。-The function is: four binary number as input, seven-segment LED on the FPGA will be 0 to F number sixteen outputs with verilog language.
ds18b20
- 在altera的FPGA上使用ds18b20温度传感器制作数字温度计，并用数码管显示。使用的语言为verilog，包含全部工程与文件，可以直接使用。-Making use of DS18B20 digital thermometer temperature sensor in the Altera FPGA, and digital tube display. The language used for the Verilog, including all the projects and fi
GP_top_restored
- 红外，超声波测距，数码管显示，蜂鸣器，用verilog语言编写-ire，and so on.
FPGA_Seg7_dsp
- 关于VHDL和verilog的数码管显示程序，写的很好，值得参考。-About VHDL and verilog digital tube display program, write well, worth considering.