搜索资源列表
i2c
- I2C协议verilog源码,包含完整的测试代码及设计文档。-Verilog source I2C protocol, including the complete test code and design documents.
book
- Verilog HDL与VHDL都是数字系统设计的硬件描述语言,VerilogHDL适合算法级,rtl,逻辑级,门级,而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware descr iption language, VerilogHDL suitable algorithm level, rtl, logic level, gate-lev
miaobiao
- 秒表功能,自带工程,EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
Design_and_verification_verilog_hdl
- 设计与验证verilog hdl配套光盘-Design and verification verilog hdl" supporting CD-ROM
ZBTSRAM
- 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
Verilog
- ADSP SHARC系列DSP应用系统设计
DigitalWatchVerilog
- 一个用Verilog实现的数字跑表的程序 希望对你的设计有帮助-With the realization of a digital stopwatch Verilog process of design you would like to help
vhdl
- :以上海地区的出租车计费器为例,利用Verilog HDL语言设计了出租车计费器,使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化,下载到EPF1OK10TC144—3芯片中,可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Veri
verilog
- 连续输入数据的课程设计 是我自己的一个课程设计希望大家能觉得好-Input data for the curriculum design
verilog
- 经典verilog实例,将近130多个。包含大部分设计基础实例,有益于初学者学习。-Classic example of verilog, nearly more than 130. Contains examples of most of the design basis, the benefit of beginners learning.
wierlesscommunicationfpgadesignmatlabverilogcode.r
- 无线通信FPGA设计的所有源码,具有良好的使用价值-verilog matlab ISE
Verilog
- verilog HDL语言使用手册,包括:语法规则,RTL设计思想和方案等-verilog HDL language user manual, including: grammar rules, RTL design ideas and programs
trafficlight
- 基于quartus 6.0的课设设计,非源码,系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
1
- 串并滤波器(FPGA源码),基于QuartusII开发设计实现的串并滤波器.-String and filter (FPGA source code), based on the achievement of development and design of QuartusII and filter string.
RD1011_rev01.2
- 采用VHDL实现的UART硬件模块,该模块包括了modem的硬件实现,已经仿真测试代码,顶层模块可以采用VHDL或verilog实现,便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog t
MPSK
- MPSK调制与解调系统设计和VHDL程序与仿真-MPSK modulation and demodulation system design and simulation of VHDL procedures and
dds_easy
- 直接频率合成DDS模块的ise工程,可以直接下载,在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波,也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位,可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram,为节省储存空间仅需要储存1/4周期的数据。根据需要,可以重新修改数据,改变波形。-DDS direct frequency synthesizer module ,ise project, can be dir
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器,由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用!-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
systemverilog
- system verilog 是国际流行的设计和验证语言,根据语言的特点分为两部分:for设计和for验证。另外一种书是介绍如何应用system verilog, 如果你要用syntem verilog, 推荐先读一下。-system verilog is popular hardware design and verification language. The languange compose of two part: systemverilog for desin , system ve
Verilog_135example
- Verilog的135个经典设计实例包括常用的程序、函数等-Verilog design 135 Classic examples include the commonly used procedure, function, etc.