搜索资源列表
Verilog
- 关于VERILOG语言的设计的中文说明书,对于初学者很有帮助,建议看一看-VERILOG language on the design of the Chinese instructions, very helpful for beginners, it is recommended to see
_8259A
- 8259A是专门为了对8085A和8086/8088进行中断控制而设计的芯片,它是可以用程序控制的中断控制器。单个的8259A能管理8级向量优先级中断。在不增加其他电路的情况下,最多可以级联成64级的向量优先级中断系统。8259A有多种工作方式,能用于各种系统。各种工作方式的设定是在初始化时通过软件进行的。 在总线控制器的控制下,8259A芯片可以处于编程状态和操作状态.编程状态是CPU使用IN或OUT指令对8259A芯片进行初始化编程的状态- 8259A is designed t
divider
- 介绍了verilog设计中一种分频器的写法,很通用实惠,方便移植-Introduced the verilog design the wording of a kind of divider, a very common benefit, to facilitate migration
lvds
- 文章介绍了lvds技术在硬件设计中的原理和应用,先已被广泛应用-This paper introduces lvds in hardware design and application of the principle, first has been widely used
verilog
- 设计可以对两个运动员赛跑计时的秒表:(1)只有时钟(clk)和一个按键(key),每按一次,key是持续一个时钟周期的高电平脉冲 (2)秒表输出用0-59的整数表示 (3)key: (A)按一下key,开始计数; (B)第一个运动员到终点时第二下key,记住时间,继续计数; (C)二个运动员到时按第三下key,停止计数; (D)然后按第四下key,秒表输出第一个运动员到终点的时间,即按第二下key时记住的计数值; (E)按第五下key,秒表清0。 -Design
Verilog_xl
- Verilog—xl很全的设计文档,能帮助在短时间内学会Verilog—xl-Verilog-xl is full of design documents, can help immediately learn Verilog-xl
基于FPGA的巴克码发生器与识别器的设计
- 详细介绍了7位巴克码以及帧同步,7位巴克码与帧同步的关系。-Details of the seven Barker code and frame synchronization, 7 Barker code and frame synchronization relationship.
sdram_controller
- SDRAM 控制器的 verilog 源代码, 针对Micron 的SDRAMS设计,支持全部的指令, 已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SDRAM controller verilog source code, for Micron' s SDRAMS designed to support all of the instructions, the logic has been verified, and actually used in chip des
VerilogProjects
- 在quartus II环境下用Verilog实现了8255, 8253, 8259, 8250, DAC0832, ADC0809等微机接口芯片,硬件设计实验课的作品,有些芯片的功能有所简化,但最基本的功能已实现,有完整的时序仿真波形-In quartus II environment achieved with Verilog 8255, 8253, 8259, 8250, DAC0832, ADC0809 and other computer interface chip, hardware
ddc
- 电子科大2009-应用于无线电监测的高速信号处理平台设计,软件无线电的DDC的FPGA实现!-UESTC 2009- applies to wireless monitoring of high-speed signal processing platform design, software radio DDC' s FPGA implementation!
yimaqi
- 计数型数码管译码器的设计,其与CD40110具有相同的功能-Counting the design of digital control decoder, which has the same function with the CD40110
FPGAdeguangshanjiancejishu
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计,用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
Verilog_shuzisheji
- 本章的目的是想通过对数字信号处理、计算(Computing)、算法和数据结构、编程语言和 程序、体系结构和硬线逻辑等基本概念的介绍,了解算法与硬线逻辑之间的关系从而引入 利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种 九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
ref-sdr-sdram-verilog
- sdram的verilog 建模参考设计,希望有所帮助-sdram and verilog implent
can
- can总线的verilog设计与实现,很好的资料哦-the implention of can bus with verilog
sin
- QUARTUSS||环境下的简易正弦信号发生器的设计,VERILOG 代码,用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
subtracter_4
- 好还是verilog,现在你记忆可以,是关于FPGA的设计-Good or verilog, now you can remember, is the design on the FPGA
Verilog-HDL
- VerilogHDL实践与应用系统设计随书代码-VerilogHDL practice and application of system design with the code book
135classic_example_of_Verilog_design
- Verilog的135个经典设计实例,由简到繁,由浅入深,值得收藏!-Verilog' s 135 classic design example, from simple to complex, Deep and worth collecting!