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Verilog-HDL--examples
- 王金明：《Verilog HDL 程序设计教程》书中的全部范例，pdf版本。-Wang Jinming: " Verilog HDL Programming Guide" all examples in the book, pdf version.
Verilog-source130
- Verilog HDL 源代码设计 一共有130个例子,欢迎下载-Verilog HDLsource130
verilog-HDL
- 蜂鸣器的FPGA设计，verilog语言，工程文件全-Buzzer FPGA-based design
verilog-code-style-specification
- 企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。-Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.
verilog-experience-for-beginners
- VerilogHDL语言的设计经验，适合初学者入门学习，包含了Verilog编写时需要注意的很多方面，很有参考价值。-VerilogHDL language of design experience, suitable for beginners to learn, including the need to pay attention when writing Verilog many aspects of great reference value.
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha
verilog
- bresenham算法是计算机图形学中为了“显示器（屏幕或打印机）系由像素构成”的这个特性而设计出来的算法，使得在求直线各点的过程中全部以整数来运算，因而大幅度提升计算速度。-Bresenham algorithm is computer graphics for display (screen or printer) is made up of pixels and the characteristics of the designed algorithm, all made in the
gpio
- 芯片设计中用于gpio传输接口之间的verilog设计，其中涉及到gpio的传输格式的所有源代码的设计-Chip design for verilog design gpio transmission interface between gpio involving transmission format all source code design
Verilog
- 这是 夏宇闻Verilog数字系统设计教程中部分例程代码，适合初学Verilog的人-This is Xia Yu smell Verilog digital system design tutorial part of the routine code, suitable for beginners of Verilog
135-classic-Verilog-design-example
- Verilog的135个经典设计实例，移位寄存器，串并转换，交通灯控制等-135 classic Verilog design example, the shift register, string and conversion, traffic light control, etc.
Verilog
- verilog数字系统设计教程，VHDL语法功能设计-verilog digital system design tutorials, VHDL syntax functional design
Frequency-divider
- 利用Verilog设计的在停车场情况下的模拟的分频器和计数器的代码-The use of Verilog design in the parking lot in case of analog frequency divider and counter code
Timing-
- 利用verilog设计的停车场中的计数器计时器和计费器，完成智能管理效果-Use the counter timer and meter parking lot in the Verilog design, intelligent management
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
verilog
- Verilogd的设计练习进阶书籍，可帮助开发人员熟练掌握编程 -Verilogd advanced design practice books, can help developers familiar with programming
VGA全驱动
- 里面有关于FPGA设计的VGA的相应实验说明，以及相关代码
verilog
- 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design
Verilog-DATAS-xiayuwen
- 3.1 引言 3.2 Verilog HDL基本结构 3.3 数据类型及常量、变量 3.4 运算符及表达式 3.5 语句 3.6 赋值语句和块语句 3.7 条件语句3.8 循环语句 3.9 结构说明语句 3.10 编译预处理语句 3.11 语句的顺序执行与并行执行 3.12 不同抽象级别的Verilog HDL模型 3.13 设计技巧-3.1 Introduction 3.2 Verilog HDL basic structure 3.3
Verilog--GUIDE
- 本指南的很多信息都围绕Verilog 的句法组织但也有另外一些有关编码标准设计流程错误保留字以及在正文按字母顺序参考部分后面的编译器伪指令系统任务和函数以及命令行选项等特殊的部分-Much of the information in this guide revolves around Verilog s syntactic organization, but there are also other coding standards that are designed to keep the