搜索资源列表
ClockOut
- 通过VERILOG编程,实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
RTL
- 256位有符号整数乘法器,个人学习时编写,接口为IPBUS,用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
sqrt32
- verilog源代码,用于开根号计算(32位)-sqrt32.v sqrt of 32-bit integer, Verilog source
dividers
- verilog格式的除法器,试过了,很好用,再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
16qam——modulation
- verilog编写的16qam调制程序,将所有东西装入工程,运行mmm16主程序。其中载波为一个周期采十个点,并乘以2^8-1取整数。在quartusII运行通过。-verilog modulation procedures 16qam prepared all things into works mmm16 to run the main program. One carrier for a cycle of 10 points taken, and multiplied by an inte
BasicRSA_latest.tar
- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman i
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
5_3
- 53整数小波滤波,编译已经成功,仿真也已经通过,是网上着的资料-53 integer wavelet filter, has been successfully compiled, the simulation has also been adopted, is online with information
verilog
- 设计可以对两个运动员赛跑计时的秒表:(1)只有时钟(clk)和一个按键(key),每按一次,key是持续一个时钟周期的高电平脉冲 (2)秒表输出用0-59的整数表示 (3)key: (A)按一下key,开始计数; (B)第一个运动员到终点时第二下key,记住时间,继续计数; (C)二个运动员到时按第三下key,停止计数; (D)然后按第四下key,秒表输出第一个运动员到终点的时间,即按第二下key时记住的计数值; (E)按第五下key,秒表清0。 -Design
etd-0407109-183702-81-001[1]
- 文章介绍了YUV向RGB颜色空间转换的硬件电路实现算法.在高基乘法算法基础上,建立了参数化高基乘法算法模型,并给出了Verilog HDL描述 小数乘法的整数乘法近似和近似误差给予了详细的讨论.采用乘法单元复用的设计结果将在两个时钟周期内完成YUV向RGB的颜色空间转换.-This paper introduces the YUV to RGB color space conversion hardware algorithm. Matrix multiplication algorithm i
BPSK
- 用于BPSK调制的自行设计,说明如下: 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵,矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时,受到前后共6个码元的共同影响,所以是由6个码元共同决定。这6个码元是随机的,可能是0也可能是1(双极性时可能是-1也可能是+1),故6个码元共2^6=64种情况,所以产生的矩阵是64*4。最后逐行输出这256个数。 2.
Verilog_integer_reg
- 深入探讨verilog中integer与reg两者的区别,从综合与实现的角度介绍-Depth in the integer and reg verilog difference between the two, from the point of introduction and implementation of comprehensive
verilog-HDL-Divider
- 两个3位二进制数的除法,结果(整数商)输出到数码管显示-Division, the result (integer quotient of two 3-bit binary number) output to the digital display
IntegerDivider
- 整数除法器 无负数复数 期末项目 verilog-integer divider
Verilog-shift-mulfunction
- FPGA verilog 实现任意位宽的移位相乘法,有符号小数或者有符号整数相乘。函数调用方式-FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call
Verilog-shift-mul
- FPGA verilog 实现任意位宽的移位相乘法,有符号小数或者有符号整数相乘非函数调用-FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication non- function call
verilog
- bresenham算法是计算机图形学中为了“显示器(屏幕或打印机)系由像素构成”的这个特性而设计出来的算法,使得在求直线各点的过程中全部以整数来运算,因而大幅度提升计算速度。-Bresenham algorithm is computer graphics for display (screen or printer) is made up of pixels and the characteristics of the designed algorithm, all made in the
float_2_int.v
- 最全的,最简单,32位浮点数转整数,32位整数转浮点数,直接可以移植,已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)
eetop.cn_利用FPGA实现浮点运算的verilog代码
- 计算机里整数和小数形式就是按普通格式进行存储,例如1024、3.1415926等等,这个没什么特点,但是这样的数精度不高,表达也不够全面,为了能够有一种数的通用表示法,就发明了浮点数。 浮点数的表示形式有点像科学计数法(*.*****×10^***),它的表示形式是0.*****×10^***,在计算机中的形式为 .***** e ±***),其中前面的星号代表定点小数,也就是整数部分为0的纯小数,后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数,例如1024就能表示成0.
vivado
- 用中规模MSI基本逻辑功能模块 实现关模比较器(要求分别使用中规模和语言实现): 功能要求:它的输入是两个8位无符号二进制整数X和Y,以及一个控制信号S;输出信号为1个8位无符号二进制整数Z。输入输出关系为:当S=1时, Z=min(X,Y);当S=0时, Z=max(X,Y)。(Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale an