搜索资源列表
simple_verilog
- cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit
i2c_slv_ctrl
- I2c总线 verilog实现，可用于quartus设计-Verilog bus I2c realized, can be used to design quartus
rs-codec(255-223)
- RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。-RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.
AppendixC_quartus
- Quartus appendix - Can be useful if you start using quartus II to code in verilog-Quartus appendix- Can be useful if you start using quartus II to code in verilog
CLK_V
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用Verilog语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. The use of Verilog language.
JIJIAQI
- Quartus II工程压缩文件，是一个典型的基于FPGA的计价器工程项目，有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
servo_module_worked
- verilog pwm to control servo motor on quartus
PWM
- verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
miaobiao
- 秒表功能，自带工程，EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
usb-blaster
- quartus多种USB-bletera 自制下载线！
FPGA_PCI_DATA
- 一个基于FPGA的PCI数据发送程序，实现从计算机通过PCI9054向FPGA发送数据功能。开发语言verilog,开发环境quartus-FPGA-based PCI data distribution process, from the computer through the PCI9054 functions to send data to the FPGA. The development of language verilog, development environment qua
trafficlight
- 基于quartus 6.0的课设设计，非源码，系统设计方案-Quartus 6.0 based on the design of the class-based, non-source, system design
quartus
- quartus中常见错误的解析以及解决办法，主要是VHDL也verilog HDL-Common Errors in quartus and the analytic solutions is mainly VHDL also verilog HDL
DE2_SD_Card_Audio(Modified)
- 在DE2开发板上实现的SD卡mp3音乐播放器。硬件部分用Verilog语言编写，在Quartus上编译；软件部分用C语言编写，在Nios2上编译运行。-DE2 development board in the realization of the SD card mp3 music player. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run
DE2_NIOS_HOST_MOUSE_VGA
- 在DE2开发板上实现的VGA输出游戏。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。把DE2板和显示器键盘连起来即可使用。-Development in the DE2 board game to achieve the VGA output. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in
DE2_NET
- 用DE2开发板实现的网络控制器。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。程序已经过测试，功能完好。-DE2 development board with the realization of the network controller. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in
123
- 基于quartus的，状态机实现流水灯，verilog HDL语言编写-Quartus-based, the state machine to achieve water lights, verilog HDL language
analogue-digi-ana-converter
- design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an ana
URAT_VHDL
- FPGA采用模块工程文件QUARTUS II工程、ADC0809、电机控制PWM、LCD12864显示控制、UART_VHDL-FPGA module QUARTUS II project engineering documents, ADC0809, motor control PWM, LCD12864 display control, UART_VHDL
pll
- 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design