搜索资源列表
quartus
- 流水灯状态机的一段式描述和二段式描述还有三段式描述的Verilog源码-Light water section of the state machine and the two-stage type descr iption descr iption descr iption of Verilog source code as well as three-
DA904_FPGA
- DAC904的FPGA驱动代码,开发环境是Verilog,quartus。所用试验板为DE0-DAC904 driver code for FPGA development environment is Verilog, quartus. The test plates used to DE0
uart
- 嵌入式串口通讯,采用verilog编写,在altera开发板上运行(Embedded serial communication, written using Verilog, altera development board on the run)
fadder_4v
- 利用quartus9.0中verilog语言实现的四位全加器,亲测有效(Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective)
CNTlum
- 使用Windows7 系统,quartus ii 9.1 软件,Verilog 语言 0到9的计数,并且亮度逐渐增大(count from 0 to 9,and the lum become more and more high)
verilogiic1121
- tvp5150视频解码,平台quartus II(tvp5150 Video decoding,quartus II)
Avgt_jesd204b_ad9250_ed
- 基于avgt开发板的jesd204b源代码,需要安装Quartus软件(Avgt development board based on the jesd204b source code)
基于FPGA的自动售货机毕业设计
- 基于FPGA的自动售货机,采用quartus 2 编写,方便可用(Vending machine based on FPGA)
pulse
- 这是一个方波程序,在quartus平台编写,可以通过设置参数生成方波信号。(This is a square wave program, written in the quartus platform, you can generate square wave signals by setting parameters.)
Verilog_Beep
- 用Verilog语言,quartus软件,实现fpga开发板上按dou lai mi fa等7个音实现按键弹钢琴(Verilog language, quartus software, to achieve fpga development board by dou lai mi fa 7 sound to achieve the key to play the piano)
Verilog_uart
- 锆石科技 用Verilog实现uart通信,文件包括模块和顶层文件,直接解压缩在quartus上编译即可。(Zircon technology Verilog with uart communication, the file includes the module and the top file, the direct decompression can be compiled on the quartus.)
DES_Core
- 基于Quartus ii 平台的DES加密算法Verilog设计和modelsim仿真(DES encryption algorithm design and Modelsim simulation based on Quartus II platform)
add
- 一个用quartus原理图输入的全加器,(A full adder with quartus schematic input,)
spram
- verilog编写的spram,包含顶层模块,控制模块和spram本体,其中spram为Altera提供的ip核,已在quartus 16上运行通过(Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16)
基于QuartusII的数字系统VerilogHDL设计实例详解
- 基于QuartusII的数字系统VerilogHDL设计实例详解(QuartusII based digital system VerilogHDL design examples)
source code
- 2.6'TFT_LCD驱动源程序,可以在quartusII平台上直接运行(2.6'TFT_LCD driver source program, you can run directly on the quartus II platform)
project2
- 基于Verilog在quartus平台上搭建的串口通信模型,适用于初学者。本实验所用RXD的波特率为9600,TXD波特率为9600×16,1位起始位,8位数据位(ASCII码),1位停止位,无奇偶校检位。接收数据时,至少连续采样8个周期都是“0”后,才认定为起始位,之后每隔16个周期取一次数据。(Verilog based on the quartus platform to build a serial communication model, suitable for beginners.
traffic2
- 数电课程设计,交通灯,基于Quartus II编写(Digital electric course design, traffic lights)
clock_shiyan
- 数电课程设计,数字时钟,基于Quartus II设计(Digital electric course design, digital clock)
mux16
- 用verilog写的乘法器,在quartus里可以直接运行,有详细注释(Multiplier written in Verilog, in quartus can run directly, with detailed notes)