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pBlazIDE36
- There are literally dozens of 8-bit microcontroller architectures and instruction sets.Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as
xapp224datarecovery
- Data recovery allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts the data from the incoming clock/data stream and then moves this data into a separate clock domain. Sometimes, the receiver
qpsk_demod_use_FPGA
- 根据软件无线电的思想，提出了一种新颖的数字信号处理算法，对QPSK信号的相位进行数字化处理，从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差，用数字锁相实现收发端载波的同步，在频偏较大的情况下，估算频偏的大小，自适应设置环路的带宽，实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台，并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点，符合未来通信技术发展的方向。-According
FPGA-FFT-design
- FPGA 实现高速 FFT 处理器的设计 介绍了采用 Xilinx 公司的 Virtex- II 系列 FPGA 设计高速 FFT 处理器的实现方法及技巧。-FPGA design to achieve high-speed FFT processor implementation methods and techniques in the design of high-speed FFT processor using Xilinx Virtex-II FPGA family.
humanpong
- 我们的目标是建立一个人力乒乓球比赛的FPGA板（Xilinx公司的Virtex-II Pro的XC2VP30与的Digilent公司VDEC1的视频解码器）。-Our group objective is to build a Human Pong game on an FPGA board (Xilinx Virtex-II Pro XC2VP30 with the Digilent VDEC1 Video Decoder).
xapp852.zip
- Xilinx Virtex5 for RLDRAM design,Xapp852 (Xilinx Design RLDRAM II Memory Interface for Virtex-5 FPGAs)
test_myip
- xilinx EDK virtex II xc2vp30 用户自定义IP核led灯实验-the xilinx EDK virtex II xc2vp30 user-defined IP core led light experiment
StopWatch
- 在Modelsim6.3c中编码，与Virtex-II Pro开发板连接实现秒表功能-In Modelsim6.3c encoding, and Virtex-II Pro development board to achieve a stopwatch function
vga_module
- VGA 显示源码。基于xilinx virtex ii 开发板开发。实现单色显示功能。-VGA display
PipelineCPU
- 设计一个32位流水线MIPS微处理器，具体要求如下： 1. 至少运行下列MIPS32指令。 ①算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令：SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 ⑤无条件跳转指令：J、JR。 ⑥数据传送指令：LW、SW
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
Video_filterinf
- Project Report-Real-time User Adjustable Video Filtering create an embedded system that demonstrates real-time video filtering using a Xilinx Virtex II multimedia board
Real-time User Adjustable Video Filtering
- Real-time User Adjustable Video Filtering aim is to create an embedded system that demonstrates real-time video filtering using a Xilinx Virtex II multimedia board
sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
verilog-radix4
- Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the embedded Virtex II FPGA’s module
DES_Triple-DES-IP-Cores
- Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
wenbenxianshi
- 用modelsim和ise开发文本显示系统。包括键盘PS2输入，SVGA视频同步，RGB处理，作者姓名显示，光标发生，图片动态显示。采用XUP Virtex-II Pro开发系统。-With modelsim and ise development text display system.Including the PS2 keyboard input, SVGA video synchronization, RGB, author name, according to the cursor,
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe
xapp223
- UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buffer for Virtex, Virtex-E and Spartan-II FPGAs-UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buf
ddr_sdram
- 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造； 支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较