搜索资源列表
XAPP134_SDRAM_Verilog
- Xilinx XAPP134 SDRAM Verilog
Xilinx-labs-manual
- a Xilinx lab manual which contains sample codes and programming techniques which are used by beginners to learn VHDL
xlx_s3a_evl-sch
- Xilinx SP3 开发板电路原理图，是学FPGA设计和电路设计的参考资料。-Xilinx SP3 development board circuit diagram, is to learn FPGA design and circuit design reference.
FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta
- FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Virtex-5EMAC
- This application note describes a system using the Virtex™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded T
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
in-ModelSim-and-Xilinx-lib
- 在ModelSim SE中配置Xilinx的库函数 在Modelsim的安装根目录下新建一个文件夹，用来放xilinx的各个库文件，故可以起名 xilinx_lib。类似于Xinlinx的安装文件：\..\\Xilinx\verilog\src中的各个库文件，在xilinx_lib文件 下新建各个文件夹，命名规则为：若src中的文件夹名为unisims，则在xilinx_lib文件夹下新建 为unisims_ver的文件夹，与此雷同，新建名为simprims_ver、Xilinx
ModelSim---Xilinx
- 很好的Xilinx编译的说明文档 CSDN的博客-Good documentation compiled Xilinx CSDN' s blog
spi_int
- realize spi interface vhdl code xilinx help ths help developers
lab2
- xilinx官网edk实验，lab2，用nexys 2 板实验源代码-xilinx edk official website experiments, lab2, with nexys 2 plate test source code
Xilinx-FPGA--PDF
- The International Seville " Xilinx FPGA Embedded System Design Senior Seminar" PDF Information-The International Seville " Xilinx FPGA Embedded System Design Senior Seminar" PDF Information
Test
- xilinx PIO示例程序源码，基于Vitex5 FPGA生成的IP。-xilinx PIO sample program source code, generated Vitex5 FPGA-based IP.
ml507_overview_setup
- xilinx 公司 ML507 开发板的入门教程，用于ML507开发板得开发
xilinx_EDK_lesson_ISE12
- Xilinx EDK 系統設計教學 使用ISE 12-Xilinx EDK lesson step by step for ISE 12
UART
- 串口VHDL程序，Xilinxṩ 测试成功。-Serial VHDL program, Xilinxṩ test was successful.
VHDL-Xilinx-ISE-a-ModelSim
- VHDL上机手册（基于Xilinx ISE & ModelSim）-VHDL-on manual (based on the Xilinx ISE & ModelSim)
mypro_synfifo
- 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
SDI_PassThr_SZ
- Xilinx SDI参考设计，Verilog/VHDL源代码和相关文档等-Xilinx SDI pass through Verilog/VHDL source code
cordicxilinx
- cordic algo in xilinx