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juanji2
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的译码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed (2,1,6) convolutional code decoding. Source and for the simulation of the test file inside
phase_test
- VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。 本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显
fft
- fft AND ifft is designed for OFDM application using CORDIC algorithm and implemented in XILINX FPGA.
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
ZedBoard_OOB_Design
- xilinx Zynq Digilent Zedboard上的可运行的Linux系统以及源码文件，有详细说明-xilinx Zynq Digilent Zedboard running Linux system as well as the source file, there is a detailed descr iption of
labsolution
- xilinx大学计划完整实验6个。非常值得学习的资料。-This is the xilinx udp labs designed with VHDL.
ISEuserguide
- ise软件使用说明，对ISE软件的掌握非常有帮助。如果你开发xilinx的FPGA,建议下载。-ise software instructions, the ISE software grasp very helpful. If you develop xilinx' s FPGA, it is recommended to download.
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
zedboard_water_flow
- xilinx的刚出板子zedboard，资料不是很多。网上也有些人做出了一些Demo。但作为新手，在操作过程中会出现各种问题。这是我做的一个Demo 的源码，和前辈一样，做了个流水灯的实验。-of xilinx' s just left the board zedboard, information is not a lot. Online some people make some Demo. However, as a novice, during operation there wi
CBPFPGA
- 很好的FPGA学习资料,不要错过，xilinx学习经典-it is good to study the FPGA
FFT
- FFT的经典实现，三重循环的蝶形运算，适合于硬件实现的软件版本，在Xilinx的Vivado仿真器下编译通过-Classic implementation of FFT software version is suitable for hardware implementation in Xilinx Vivado emulator compiled by
verilog
- it is xilinx SDR SDRAM controller core
V5
- xilinxFPGA v5的手册，十分详细，有利于初学者来学习xilinx的FPGA使用方法。-xilinxFPGA v5 manual is very detailed, is conducive to beginners to learn xilinx FPGA use.
Virtex-5-Family-Overview
- 本文是xilinx fpga v5芯片家族的整体介绍，famliy view-This article is xilinx fpga v5 overall introduction of the chip family, famliy view
RocketIO-GTX-Transceiver-User-Guide
- 本文基于xilinx fpga v5 ，主要介绍rocket io的使用-This article is based the xilinx fpga v5, introduced the use of the rocket io
Virtex-5-FPGA-PCB-Designers-Guide
- 本文基于xilinx fpga v5,主要介绍制作PCB时的一些事项-This article is based the xilinx fpga v5, introduces some of the issues when making PCB
humanpong
- 我们的目标是建立一个人力乒乓球比赛的FPGA板（Xilinx公司的Virtex-II Pro的XC2VP30与的Digilent公司VDEC1的视频解码器）。-Our group objective is to build a Human Pong game on an FPGA board (Xilinx Virtex-II Pro XC2VP30 with the Digilent VDEC1 Video Decoder).
xilinx_hwicap
- linux Source code, This is the code behind /dev/icap -- it allows a user-space application to use the Xilinx ICAP subsystem. -linux Source code, This is the code behind /dev/icap -- it allows a user-space application to use the Xilinx ICAP subsystem
OZ745
- 4k*2K zynq The OZ745 is a video development platform based around the Xilinx® Zynq-7045 FPGA. The kit includes all the basic components of hardware, design tools, IP, pre-verified reference designs and Board Support Package to rapidly devel
mult32
- 4-cycle 32bit-Multiplier that can be work in FPGA. Correct work is confirmed by SP605 FPGA from Xilinx.