搜索资源列表
ds18b20_20130712
- 基于XILINX VERTEX-5的ds18b20温度传感器的状态机控制，使用状态机对一线传感器进行控制，用示波器进行观察。-The design is based on the xilinx vertex-5 aimed to realizing the goal of detecting the temperature through ds18b20.
CH7301
- Xilinx microblaze下配置CH7301 RGB转DVI芯片的程序，程序正确，验证过！-Xilinx microblaze configure CH7301 RGB to DVI chip program, the program is correct, verified!
ml605_FMC_Si570_Prog_rdf0047_13.4_c
- 该源码是基于xilinx ml605开发板扩展接口FMC的设计，在开发板中插入子卡，程序在开发板中测试通过。-The source is based on xilinx ml605 development board FMC expansion interface design, the development board daughter card is inserted, the program development board test.
ml605_MIG_rdf0011_13.4_c
- 该参考程序是基于xilinx ml605开发板的一个DDR3参考设计，源文件包含相应的管脚约束文件。-The reference procedure is based on xilinx ml605 development board a DDR3 reference design source file contains the corresponding pin constraint file.
irig_b
- 用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，-Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,
1111
- Xilinx FPGA设计DDR2接口的方法PPT，介绍的非常详细，值得参考。 -Xilinx FPGA DDR2 interface design method PPT, described in great detail, it is worth reference.
v6Integrated-Block-for-PCIE-UG
- 赛灵思官方公布的PCIE集成端点核设计用户指导，是FPGA从业者的好帮手-Xilinx Integrated Endpoint official PCIE core design user guide, is a good helper for FPGA practitioners
xilinx_pci_exp_downstream_port
- //-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved. //-- This text contains proprietary, confidential //-- information of Xilinx, Inc., is distributed //-- under license from Xilinx, Inc., and may be used, //-- copied and/or disclosed
flipflop_d
- Xilinx Verilog D触发器 绝对好用-Xilinx Verilog D flip-flop is absolutely easy
FIFO
- 这是一个在xilinx下运行的关于FIFO的IP核设计的程序。-This is a run on the FIFO xilinx IP core design process.
LTE-xilinx_PFGA_reference_design
- xilinx中一整套关于LTE在FPGA下的解决方案，里面涉及到LTE设计的L1层和L2层以及结合其硬件的设计方案和内容，非常利于LTE开发-xilinx set on the LTE solution under the FPGA, which relates to the design of LTE L1 and L2 layers and the combination of the hardware design and content development is beneficial
LTE-xilinx_PFGA_reference_design_all
- xilinx中一整套关于LTE在FPGA下的解决方案，里面涉及到LTE设计的L1层和L2层以及结合其硬件的设计方案和内容，非常利于LTE开发-xilinx set on the LTE solution under the FPGA, which relates to the design of LTE L1 and L2 layers and the combination of the hardware design and content development is beneficial
vga_block2
- 一个xilinx工程，自己做的，主要是在VGA上显示一个动态方块，在屏幕上自由移动，碰壁反弹-A xilinx project, do it yourself, is mainly a dynamic display box on the VGA, freedom of movement on the screen, snags a rebound
HCSR04
- 超声波传感器的工作原理，这里的超声波指的是用在xilinx zynq7000开发板上的传感器。-The working principle of the ultrasonic sensor in this case, the ultrasonic wave is used in xilinx zynq7000 sensors on the development board
FRFT_Ozaktas
- 这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序，FPGA是Xilinx的virtecx-5，这是我在做毕业设计的时候自己编写的，希望能对你有帮助！-This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate desi
Puzzle
- 一个用verilog编写的VGA显示拼图游戏，本程序基于Xilinx的Basys2开发板，图像存储于ROM中-A VGA display jigsaw puzzle with verilog written, the program is based on the Basys2 Xilinx development boards, the image is stored in ROM
deinterlace
- Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx offers a way to use line cache interpolation of interlaced programs line by line, than the general algorithm effect is a great improvement.
cfcard
- 这是xilinx v2开发板cf卡读图片的程序。用c语言编写。在xilinx官方网站上有cf可读图片的工程，再将这段代码加载进去就可以了。这是个调试成功的程序。-This is a development board xilinx v2 picture cf card reading process. With c language. In the Xilinx website have cf readable picture works, then the code is loaded int
evodem_mppt_son_hali_OK
- This my complete simulink project using xilinx system generator blocks. There is a buck converter and a control unit for FPGA calculating MPPT to get maximum power from the PV panel. MPPT calculation is done using sysgen blocks. Also HWCOSI
LogiCORE-IP-Video-Scaler-v4.0
- The Xilinx Video Scaler LogiCORE™ IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.