搜索资源列表
RS232_R_T
- 基于FPGA的verilog语言的串口通讯的数据接收和发送模块的程序-The data receiving and sending module of FPGA serial communication program based on Verilog language.
CycloneII-VerilogV
- Altra CyloneII Verilog文件，共有18个工程，包括标准键盘、串口、VGA、EEPROM、LCD1602等操作源码-Altra CyloneII Verilog files,include keyboar.com.VGA、EEPROM、LCD1602 operation surce codes
uartverilog
- verilog实现串口的传输,希望verilog的初学者有所帮助。-serial transmission verilog, verilog hope to help beginners.
serial-port-communication
- 实现串口通信的verilog代码，简述基本串口通信功能的实现-serial port communication verilog code
Uart
- 用Verilog实现简单的串口通信，经过功能仿真和板上调试，接收和发送模块均无问题-Using Verilog realize a simple serial communication, through functional simulation and on-board debugging, had no problems receiving and sending module
uart_test
- 串口传输 verilog 实现
uart_fifo
- 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
QUARTUS_WORK_FORTH
- 基于verilog语言的，FPGA程序实现电脑与FPGA串口的数字传输，硬件设备为EP1C3T100C8，usb转RS232芯片为FT232BM，-Based verilog language, FPGA program FPGA serial digital transmission of computer and hardware devices to EP1C3T100C8, usb to RS232 chip FT232BM,
uart_loop
- 串口通信,采用verilog实现串口通信程序-uart,Serial communication
uart_verilog
- QII - VERILOG 精品串口源码，有多种不同设置，数据位、停止位、检验位可调。-QII- VERILOG boutique serial source, there are a variety of different settings, data bits, stop bits, parity bit adjustable.
rtl
- 通过verilog实现pc串口和fpga的双向通信。代码是老外写的，非常严谨-the verilog code comnunicate with the pc by serial port
uart_async
- RS232串口通信代码，采用verilog HDL实现，在quartus上仿真通过并下载到fpga平台功能验证-RS232 CODE
uart
- 基于RS232的串口通信 源代码-UART base on rs232 verilog files
RS_232_2
- RS232串口通讯实验，verilog HDL，在quartusII开发环境下-RS232 serial communication experiment, verilog HDL, in quartusII development environment
uart_latest.tar
- 串口（UART）的verilog源代码，可以供设计参考-Serial port (UART) of the Verilog source code, can be used for reference in design
UART3
- 基于verilog语言编写的串口通信程序-verilog
FPGA_Uart
- FPGA程序，verilog HDL语言编写，包含AD转换和串口发送程序，由于AD芯片种类繁多时序迥异，故主要参考串口发送程序。本程序使用quartus ii 13.0 编写。-FPGA procedures, verilog HDL language, includes an AD converter and serial transmission program, since a wide range of AD chip timing are different, so the main
AD7606URAT
- Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。-Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.
uart14312413242
- 串口发送与接收Verilog错误代码
verilogUART
- Uart串口程序，rs232,Verilog语言编写,-Uart serial program, rs232, Verilog language,