搜索资源列表
ps2
- 用VHDL语言实现了PS/2通信协议，PS/2是一种双向同步的串行通信协议。-VHDL language using a PS/2 communication protocol, PS/2 is a two-way synchronous serial communication protocol.
8-bitinput-output-shift
- 8位串行输入，串行输出移位寄存器 VHDL-8-bit serial input, serial output shift register VHDL
UART
- xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
jieshou
- 实现异步串行通信的接受部分，采用vhdl语言实现-Acceptance of asynchronous serial communication part, using vhdl language
send
- 采用vhdl语言编程，实现异步串行通信的发送自己定义的通信协议格式-Using vhdl language programming, asynchronous serial communication to send their own communication protocol format definition
Serial
- VHDL语言的串行通讯程序，已调试过了可以下载使用-VHDL language serial communication program, you can download have been used to debug
Proj
- verilog/vhdl 串行口232通信程序-Spartan3E开发板调试通过-verilog/vhdl serial port communication program-Spartan3E 232 development board debugging
UART_final
- 利用vhdl硬件描述语言，模拟异步通用串行接口UART的通信方式，已在fpga上实际测试，通信性能不错，有一定的参考学习价值！-Using vhdl hardware descr iption language, simulated UART asynchronous serial interface common means of communication, the actual test in fpga, communication performance is good, there i
handset
- 利用硬件描述语言vhdl模拟实现与9针ps2手柄的串行通信，完成手柄输入信号的采集。-Vhdl simulation using hardware descr iption language to achieve ps2 with 9-pin serial communication handle, the handle to complete the input signal acquisition.
SPI_Verilog
- SPI串行总线接口的VHDL代码，详细讲解实现过程。-SPI serial bus interface VHDL realization elaborate on the realization of the process.
24BitDigIO
- 使用Quartus设计的，串行方式控制，24位数字输入输出的程序。-VHDL 24bitIO
parallel_in_serial_out
- 适用于D/Atlc5620的并行-串行数据转换模块【VHDL】-parallel_in_serial_out driver for D/Atlc5620【VHDL】
VHDL_design
- 以VHDL设计一有限状态机构成的序列检测器。序列检测器是用来检测一组或多组序列信号的电路，要求当检测器连续收到一组串行码（如1110010）后，输出为1，否则输出为0。-With VHDL Design into a finite state machine sequence detector. Sequence detector is used to detect the signal sequence of one or more groups of circuits, require th
eda
- 本实验目标是利用FPGA逻辑资源，编程设计实现一个串行通用异步收发器。实验器件为“创新综合实验平台”上集成的Altera NIOSII开发板，FPGA芯片型号为EP1C12F324C8。电路设计采用VHDL硬件描述语言编程实现，开发软件为QuartusII6.0。-The goal is to use the FPGA logic resources, programming design realize a serial general asynchronous transceiver. Th
Phoenix3
- 数字密码锁的VHDL语言八位二进制，串行输入，有开锁和错误提示（LED） -code lock
lock
- 基于VHDL的4位电子密码锁，可以进行密码输入，更改，锁定，解锁。密码输入和输出都是串行的。-4 of VHDL-based electronic lock, password input, change, lock and unlock. Password input and output are serial.
Serial
- 通过用VHDL语言设计串行扫描显示电路进一步掌握使用VHDL方法-Display circuit with a serial scan of the VHDL language to further understand the use of VHDL method
screw
- 基于FPGA的串行数据加解扰代码，用VHDL实现，可跑400M的速度。-FPGA-based serial data plus descrambling code using VHDL, and can run 400M speed.
atel2_bin
- 串行口 VHDL 嵌入式 单片机 串行接口实现-serial port
SHIFT8
- 基于FPGA的串行输入并行输出寄存器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA serial input parallel output the design of the register, QuartusII compile, USES the VHDL language.