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traffic
- 接口如下所示:clk:时钟输入端,此信号是串行扫描的同步信号; data_control[7..0]:8个分别控制数码管显示的输入信号; led_addr[7..0]:对8个数码管进行串行扫描的输出控制信号; seg7_data[6..0]驱动7段数码管各显示段的输出信号; -VHDL programing
fir8
- 用verilog编写的8阶串行fir滤波器-verilog vhdl fir
FPGA
- FPGA和单片机串行通信接口的实现,VHDL的源代码。-And single-chip FPGA realization of serial communication interface, VHDL source code.
Sim_SDAIN
- 并行数据转换串行数据发生VHDL程序,需要的同志可以看看是否可以用 自己写的-Serial data in parallel data conversion process occurred in VHDL, the comrades need to see if it can be written in their own
yiwei2
- 16位并行数据转换成串行数据,适用于FPGA与单片几之间的通信问题 (VHDL 编程)-FPGA VHDL
tongxunjiekou
- 基于VHDL语言,实现串行通讯接口功能的主程序-The use of VHDL language implementation of the serial communication interface program
FIRFIR1
- 基于FPGA的FIR串行滤波器设计与实现,本文运用VHDL编写-FPGA-based FIR filter design and implementation of the serial, the paper prepared by the use of VHDL
zy4668_ybcxjk
- 本源码实现的功能是用VHDL编写异步串行接口设计-The source VHDL implementation of the function is the preparation of Asynchronous Serial Interface
8bitadder
- 串行8位加法器工程,已编译成功.标准代码VHDL语言-Serial 8-bit adder works have been compiled successfully
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源(20位m序列),crc编码(采用串行算法),加噪(用22位m序列产生稀疏的1,然后和编码后的数据异或)。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se
communications_2
- 用vhdl代码描述的通信系统仿真程序。包括信源(20位m序列),crc编码(采用串行算法),加噪(用22位m序列产生稀疏的1,然后和编码后的数据异或),crc解码,数据串行输出。 -Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), no
Exp5_UART
- 用VHDL在SOPC试验箱中实现异步串行通讯转换,用VHDL硬件描述语言实现处理器CPU
uart-txblock
- vhdl实现了UART的数据发送,将八位并行数据转成串行数据输出,并加上起始位和奇偶校验位,停止位。-vhdl UART data transmission realized, the eight parallel data into serial data output, plus the start bit and parity bits, stop bits.
Serial
- 基于epm1270的串行通信vhdl代码-serial vhdl code for epm1270
eda-2009
- 9600波特率的串行口VHDL接收和发送模块,两个模块既可以单独使用。-VHDL 9600 baud serial port receive and transmit modules, two modules can be used alone.
sipo_reg5
- VHDL语言描述具有同步清零的5位串行输入并行输出移位寄存器代码-VHDL language to describe the clearing of 5 with synchronous serial input parallel output shift register code
VHDL1
- 一种利用CPLD实现波特率自动侦测的方法,介绍了数据接收模块系统,分析了波特率自动侦测原理,利用VHDL语言对其进行了编程,最后给出了仿真结果,从而推广该方法的应用。 关键词:串行通信,波特率,自动侦测,仿真结果 -CPLD realization of a use of automatic baud rate detection methodology, the data receiving module systems, analysis of the principle of au
EDA_reg
- 并行数据串行数据的VHDL程序,需要的可以看看。-VHDL serial data parallel program data, the need to look at.
Source
- 使用VHDL基于CPLD的源程序,程序的功能是做时钟的X分频,输出串行码-CPLD using VHDL source program based on the program' s function is to do X clock frequency, the output serial code
uart
- 串行异步收发接口,简称UART,是一种广泛应用的串行传输接口。这是用vhdl实现的程序,将UART分成相应的几个模块,并用顶层文件进行模块化设计。-Send and receive asynchronous serial interface, referred to as the UART, is a widely used serial transmission interface. This is achieved using vhdl procedure to the appropriat