搜索资源列表
divideVerilog
- 在FPGA上编写的快速乘法器、可用于综合等模块-fast divide\
multiply
- vhdl语言编写，实现了任意位数的两个数的乘法器-Realize any two-digit number of multiplier
PFC10
- PFC功率因素校正电路，基于乘法器的APFC-PFC power factor correction circuit, multiplier-based APFC
VerilogSourceCode
- 乘法器、除法器、多路选择器、编码器、BCD码转换、加法器、减法器、状态机、四位比较器、数码管、串口、跑马灯、电子钟-Multiplier, divider, multiplexer, encoder, BCD code converter, adder, subtractor, state machines, four more players, digital control, serial port, marquees, electronic clock
93317478verilog.HDL.examples
- FIFO,加法器，乘法器的VERILOG语言-fifo
mux
- 本例实现的功能是一个16位的乘法器，并增加了仿真代码-In this case the function is to achieve a 16-bit multiplier, and to increase the simulation code
4BITMULTIvhdl
- 4BIT MULTI VHDL乘法器4位元VHDL實現-4BIT MULTI VHDL
booth
- 一个booth乘法器的小例子, 有助于理解booth算法-An example for a booth multiplier in Verilog HDL
muil
- 基于verilog的乘法器 简单实用 初学者的好材料-Verilog multiplier based on simple and practical good material for beginners
chengfaqi
- 一个乘法器，比较简单，但也是自己认真写的，上传上来了-hahahhahhahha
mulhoulai
- 这是一个乘法器的Verilog实现，这是仿真AMR处理器核中的乘法器开发的。挺不错的。-It is a multiplier using the Verilog.
Multiplier
- 使用三种不同结构（加法树、查找表、Booth算法）实现的乘法器，带有测试文件。-Use of three different structures (addition tree, look-up table, Booth algorithm) to achieve the multiplier, with testbench files.
MUX16
- 基于VerilogHDL的简易的16位以为累加乘法器，包括乘法器模块和测试模块，已经通过仿真测试。-Based on the simple VerilogHDL that the cumulative 16-bit multiplier, including the multiplier module and test module has been tested by simulation.
simple_multiplication_calculator
- 代码是关于一个简单的乘法器在VC++2008平台上的全部源代码。你可以自己运行修改。-the folder including all the resource codes of a simple multiplication calculater run on the VC2008,you can modify it for using in your programs.I hope it can be helpful for you.
multiplier
- 采用移位相加方法设计的串行乘法器，具有握手信号（输入启动信号，输出完成信号），采用状态机方法设计的源代码。-A serial multiplier with a handshake signals (input start signal, the output completion signal), designed by adder and shifter using a state machine.
8multipler
- 用VHDL实现8位移位相加乘法器，从被乘数的最低位开始，若为1，则乘数左移后与上次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。-VHDL 8-bit shift by adding the multiplier to achieve, starting from the lowest multiplicand, if 1, then left after the multiplier and add the last if 0, left after adding all 0, u
multiplier_10_1
- 乘法器（被乘数、乘数均为4bits,经仿真通过）-This is a code of multiplier with both 4_bit multipliand and 4-bit multiplier.The code has been simulated successfully.
chengfaqi.doc
- 设计一个两个5位数相乘的乘法器。用发光二极管显示输入数值，用7段显示器显示结果。乘数和被乘数分两次输入(verilog语言实现)-Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input
ff_mul
- 基于rs编码器的verilog伽罗华域乘法器设计-Rs encoder based on Galois field multiplier verilog
Mul16
- 16位高速乘法器,采用booth编码，华莱士压缩，超前进位加法器求和完成-16-bits Multiplier