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example1
- 实现一个将时钟信号CLK十分频的功能，可以通过波形仿真来看效果。-The realization of a clock signal CLK is the frequency of the function, you can look at the effect of waveform simulation.
example1
- 本例程属于独立实验，主要是让大家熟悉一下VHDL 语言基本语法，这是比较简单的 程序了。实现一个将时钟信号clk 十分频的功能，可以通过波形仿真来看效果。 波形仿真的过程可以参考视频“波形仿真.exe”文件，有比较详细的操作方法。其实 在例程的项目中已经包含了波形仿真文件，大家可以直接仿真，观察结果。 -This routine is an independent experiment is designed to allow you familiarize yourself
example1
- 实现将时钟信号clk十分频的功能，可通过波形仿真来看效果。-To achieve the clock signal clk is the frequency function is available through the waveform simulation to evaluate the effects.
dsss-and-fhss-examples
- 本文件包含了两个直扩和跳频的例子，用MATLAB语言实现，而且还包括例子的原文及大量注释，十分详细-This document contains two examples of DS and FH, with the MATLAB language, but also examples of the original and a lot of notes, very detailed
divide_10
- 十分频 quartus实现 有RTL图-RTL is a graph realization of the frequency quartus
2010011022
- 在电子领域内，频率是一种最基本的参数，并与其他许多电参量的测量方案和测量结果都有着十分密切的关系。由于频率信号抗干扰能力强、易于传输，可以获得较高的测量精度。因此，频率的测量就显得尤为重要，测频方法的研究越来越受到重视。 频率计作为测量仪器的一种，常称为电子计数器，它的基本功能是测量信号的频率和周期频率计的应用范围很广，它不仅应用于一般的简单仪器测量，而且还广泛应用于教学、科研、高精度仪器测量、工业控制等其它领域。在数字电路中，数字频率计属于时序电路，它主要由具有记忆功能的触发器构成。在
example1
- 分频程序：实现一个将时钟信号clk十分频的功能-Frequency program: to achieve a frequency of the clock signal clk is the function of
div
- 我做的一个用VHDL语言的十分频程序，已通过验证，简单易学-I do a very frequent use VHDL language program, has been validated, easy to learn
Frequencylockloop
- 仿真GPS接收机中的锁频环功能，与硬件设计十分相似，稍作改动即可实现锁相环功能-Simulation of GPS receiver in frequency-locked loop functions, and hardware design is very similar, minor modifications to achieve phase-locked loop function
sasi-fr_div
- 分频器——十分频。每十个时钟脉冲就输出一个脉冲-Divider- very frequent. Every ten clock pulses output a pulse
CPLDfrequency
- 频率计CPLD模块。主要实现多次十分频，对各位频率进行计数。锁存和清零功能-Frequency counter:function as a frequency division. counter each bit. latch and clear
gray
- verilog语言编写的十分频器源码和测试文件-a program of ten divider,with a source and test file,using the verilog language
pulse10
- VHDL十分频程序源代码。简单修改代码中的值就可以得到其他分频。-VHDL is very frequency of program source code. Simple to modify the code in the value you can get other divider.
clk-10divide
- 十分频，用verilog语言编写的程序，使用与verilog学习。-The very frequency, the Verilog language program, the use of learning verilog.
cymometer
- 硬件频率计的实现，包括十分频，门控信号产生，频率测量等-cymometer implementation， involving 10 times divider, generating gate controling signal and frequency measurement
clk-10divide
- 基于verilog编写的十分频时钟，简单易懂，欢迎大家下载和学习-Based on the frequency counter verilog prepared very easy to understand, are welcome to download and learn
包络分析VI
- 在频域分析中，包络谱分析是一种十分有效的信号处理手段。利用包络谱分析能够准确得出故障频率，能够直观判断故障类型。本文件将包络谱分析直接做成了一个子VI，方便信号处理程序直接调用。(In frequency domain analysis, envelope spectrum analysis is a very effective signal processing method. The fault frequency can be accurately obtained by using e
devider10
- 实现对时钟信号的二分频和十分频，二者作为系统的两个输出(Realization of two frequency division and ten frequency division of clock signal,and the two are used as the two output of the system.)
SCFDE
- 该算法是迄今为止我找到的最好的最完整的单载波频域均衡的原理。众所周知，时域均衡一直是接收机的瓶颈能估，频域均衡则要简单的多。频域均衡使用基于块传输的机制，类似于OFDM，并且是单载波的。接收机十分完整，包含载波同步、帧同步等，最重要的均衡处理。(This algorithm is the best and the most complete single carrier frequency domain equalization principle I have found so far. As
频率计实验程序代码
- XC7A35TCSG324-1的Verilog频率计程序，支持十分频，支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)