搜索资源列表
EDACLOCK
- 用VHDL语言编写数字钟的程序，实现数字钟的完整功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
TIMER.rar
- 数字钟 六位数码管显示，有清零端，采用分层设计方式编写,6 digital tube digital clock showed that zero-side, using hierarchical design approach to the preparation of
clock_verilog.rar
- verilog语言实现的数字钟，各种定时闹钟功能类似真实的表~利用EDA实验平台实现~~,Verilog language implementation of the digital clock, alarm clock features a variety of regular table similar to the real experimental platform ~ using EDA implementation ~ ~
LED-clock.rar
- 采用DS1302的数码管数字钟，简单实用（程序标注详细）,Using the DS1302 digital tube digital clock, simple and practical (tagging procedure in detail)
a.rar
- 微机接口课程设计 数字钟实验 源代码 8255 8259 led显示 键盘,Computer Interface curriculum design, digital clock experiments show the source code 8255 8259 led keypad
Single-chip-digital-clock
- 单片机数字钟，实现时分秒的LED显示，以及闹钟功能，起参数可以根据需要自己调，供实验参考-Single-chip digital clock, minutes and seconds to achieve the LED display, and alarm clock function, since their parameters can be adjusted as needed for the test reference
mcu
- 基于单片机的数字温度计和数字钟设计,基于单片机的数字温度计和数字钟设计-Microcontroller-based digital thermometer and digital clock, microcontroller-based digital thermometer and digital clock design
VHDL_clock
- 关于电子数字钟得FPGA实现，上传来分享一下-Electronic digital clock was on the FPGA, upload to share with you
kt3tuo
- 基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯-Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
51chengxu
- 51单片机程序-数字钟加上用继电器连接控制的小灯泡-51 SCM program- with a digital clock with a small light bulb connection control relays
DS1302
- 基于STC89C52的DS1302的数字钟-The DS1302 digital clock based STC89C52
multisim
- 这是多功能数字钟的文档，用Multisim10开发，有原理图以及说明。-This is a multi-functional digital clock document, with Multisim10 development, there is schematic and instructions.
shuzizhong
- STC52芯片做的数字钟，8位共阳数码管，可设置闹铃，秒表等-clock
6
- verilog 写的 多功能数字钟-verilog to write multi-functional digital clock
clock.c
- 数字钟程序*** * 六位数码管 显示HH.MM.SS(时分秒),MM.DD-W(月日-星期),闹钟定时时间 **************** //****** 按键S5依次选择调整时间-显示月日星期-调整月日星期-显示闹钟定时时间-调整闹钟定时***** //****** 按键S2依次选中时分秒(月日星期)数码管,S3按键依次加1,S4按键依次减1 ****************************** //****** 整点报时,闹钟功能-clock
NiosII_clock
- 用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
eda-chengxu
- VHDL语言源程序，使用元件例化的方法设计简易数字钟-VHDL language source code, the use of components instantiated designed simple digital clock
DigitalClock
- 单片机数字钟设计，采用PROTEUS仿真-digital clock design
aa
- 数字钟程序 数字钟程序数字钟序数字钟程序-Digital Clock Digital Clock procedure procedure sequence digital clock digital clock procedures
dzagree
- 16位按键扫描程序,包含数字钟计时,闹钟报警,及定时应用-16 button scanning procedures, including digital clock timer, alarm clock, alarm, and timing applications